A Study on Reconstructing Memory Hierarchy that Utilizes Emerging Devices
| Project/Area Number |
23650026
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Fukuoka University |
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Principal Investigator |
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| Project Period (FY) |
2011 – 2013
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
Fiscal Year 2013: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2012: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2011: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
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| Keywords | 計算機システム / システムオンチップ / ハイパフォーマンス・コンピューティング / フラッシュメモリ / 相変化メモリ |
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| Research Abstract |
Processor performance is still improved in order to achieve increasing performance demand. However, computer system can not provide us with enough performance to meet the demand. This is due to the poor performance of memory system. In addition, memory consumes huge power. Considering the above, we started our project.
We assume that we can use next-generation memory devices such as STT-MRAM. Under this assumption, we try to reconstruct memory hierarchy in order to achieve high-performance, low-power, and dependable memory system.
The proposed memory system can improve energy-delay product by up to 49%.
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Report
(4 results)
Research Products
(23 results)
