Task Mapping for Hierarchical Many-core Processors in Embedded Systems
Project/Area Number |
24500058
|
Research Category |
Grant-in-Aid for Scientific Research (C)
|
Allocation Type | Multi-year Fund |
Section | 一般 |
Research Field |
Computer system/Network
|
Research Institution | Nagoya University |
Principal Investigator |
EDAHIRO MASATO 名古屋大学, 情報科学研究科, 教授 (50578854)
|
Research Collaborator |
ABRADANI Sou
|
Project Period (FY) |
2012-04-01 – 2015-03-31
|
Project Status |
Completed (Fiscal Year 2014)
|
Budget Amount *help |
¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000)
Fiscal Year 2014: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2013: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
|
Keywords | 組込みシステム / マルチコア / メニーコア / タスク配置 |
Outline of Final Research Achievements |
In this research, we proposed a task mapping method that considers features of task graphs and performance characteristics of hierarchical many-core architectures. We proposed the "HCME" toward task mapping method for "CMesh" which is a type of hierarchical many-core architectures. We also proposed a merge technique required when there are more number of tasks than the number of cores. We compared our proposed mapping method with existing algorithms. As a result of evaluation experiments, our proposed method reduced communication cost and application completion time.
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Report
(4 results)
Research Products
(4 results)
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[Presentation] 情報処理学会2014
Author(s)
油谷 創,枝廣 正人
Organizer
第34回組込みシステム研究発表会
Place of Presentation
札幌
Year and Date
2014-09-17
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