Design and evaluation of design-for-testability circuits for delay faults using built-in time-to-digital converter
| Project/Area Number |
24500067
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | The University of Tokushima |
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Principal Investigator |
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| Project Period (FY) |
2012-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2014: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2012: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
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| Keywords | VLSIの検査技術 / 検査容易化設計 / 遅延故障 / テスト生成 / VLSI / ディペンダブル・コンピューティング / LSIテスト / ＶＬＳＩの検査技術 |
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| Outline of Final Research Achievements |
Testing delay faults caused by defects like opens and shorts is more important to ensure test quality in recent highly integrated circuits. In this research, we propose design-for-testability circuits for detecting delay faults in both inside of LSI chips and interconnection between chips. The proposed design embeds a time-to-digital converter into a chip that can observe the delay of transition signals. We evaluate feasibility to detect delay faults by the proposed design using simulation and the experimental ICs. The condition for testing delays of two or more paths and the size of detectable delay faults are also evaluated to show the effectiveness of the proposed method.
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Report
(4 results)
Research Products
(16 results)
