Research on low power mixed signal LSI with novel quantizer
Project/Area Number |
25420345
|
Research Category |
Grant-in-Aid for Scientific Research (C)
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Allocation Type | Multi-year Fund |
Section | 一般 |
Research Field |
Electron device/Electronic equipment
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Research Institution | Tokyo City University |
Principal Investigator |
SAN HAO 東京都市大学, 知識工学部, 准教授 (30400774)
|
Project Period (FY) |
2013-04-01 – 2016-03-31
|
Project Status |
Completed (Fiscal Year 2015)
|
Budget Amount *help |
¥5,070,000 (Direct Cost: ¥3,900,000、Indirect Cost: ¥1,170,000)
Fiscal Year 2015: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2014: ¥3,120,000 (Direct Cost: ¥2,400,000、Indirect Cost: ¥720,000)
Fiscal Year 2013: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
|
Keywords | ADC / アナログ集積回路 / 集積回路 / AD変換器回路 / 混載信号処理回路 / AD変換回路 |
Outline of Final Research Achievements |
This research propose a novel mixed signal processing LSI of multi-bit ΔAD modulator for low power and high signal-to-noise-and distortion (SNDR) application. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feedforward modulator is realized by a passive-adder embedded successive approximation register (SAR) analog-to-digital converter (ADC) which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power at all when a preamplifier is not used. Proposed modulator is fabricated in TSMC 90nm CMOS technology. Measurement results show the feasibility of proposed circuit architecture.
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Report
(4 results)
Research Products
(9 results)