| Project/Area Number |
26280044
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Partial Multi-year Fund |
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| Section | 一般 |
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| Research Field |
High performance computing
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| Research Institution | Kyoto University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
岩下 武史 北海道大学, 情報基盤センター, 教授 (30324685)
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| Co-Investigator(Renkei-kenkyūsha) |
HIRAISHI TASUKU 京都大学, 学術情報メディアセンター, 助教 (60528222)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥16,770,000 (Direct Cost: ¥12,900,000、Indirect Cost: ¥3,870,000)
Fiscal Year 2016: ¥5,460,000 (Direct Cost: ¥4,200,000、Indirect Cost: ¥1,260,000)
Fiscal Year 2015: ¥5,330,000 (Direct Cost: ¥4,100,000、Indirect Cost: ¥1,230,000)
Fiscal Year 2014: ¥5,980,000 (Direct Cost: ¥4,600,000、Indirect Cost: ¥1,380,000)
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| Keywords | 並列処理 / メニーコアプロセッサ / プログラム変換 |
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| Outline of Final Research Achievements |
We have pursued the research on three elemental technologies, namely cache-aware code generation, loop transformation for SIMD-vectorization and computation-communication pipelining, for high-performance application development targeting manycore processors. These technologies and our development framework were applied to practical high-performance applications such as supersonic propagation analysis, PIC plasma simulation, and various linear solvers. The importance and effectiveness of our research work were proved by the results of, for example, PIC plasma simulation whose single-processor performance improvement is 8-fold and 64-node performance is 10-times as high as that of a multi-core based system.
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