VLSI Implementation of Generic Hardware for Machine Learning
Project/Area Number |
26330065
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Research Category |
Grant-in-Aid for Scientific Research (C)
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Allocation Type | Multi-year Fund |
Section | 一般 |
Research Field |
Computer system
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Research Institution | Osaka University |
Principal Investigator |
Onoye Takao 大阪大学, 情報科学研究科, 教授 (60252590)
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Project Period (FY) |
2014-04-01 – 2017-03-31
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Project Status |
Completed (Fiscal Year 2016)
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Budget Amount *help |
¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2016: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2015: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2014: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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Keywords | 機械学習 / VLSI / アーキテクチャ |
Outline of Final Research Achievements |
In this research, design of generic hardware for high speed classification in machine learning is proposed with providing flexible adaptability of its hardware organization. Specifically, a Support Vector Machine, which has inherent versatility for applications is accelerated by soft-cascade processing while maintaining its classification capability. Dimension of feature vectors and bit precision in calculation can be controlled without re-designing hardware. VLSI implementation is coordinated with the use of FPGA and 45nm technology to confirm the ability of adaptive reconfiguration. The designed FPGA and 45nm circuit attain 79VGA frames/7HD frames processing and 361VGA frames/35HD frames processing per second, respectively.
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Report
(4 results)
Research Products
(11 results)
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[Journal Article] Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing2014
Author(s)
H. Konoura,D. Alnajjar,Y. Mitsuyama,H. Shimada,K. Kobayashi,H. Kanbara,H. Ochi,T. Imagawa,K. Wakabayashi,M. Hashimoto,T. Onoye,H. Onodera
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Journal Title
IEICE Trans. on Fundamentals
Volume: E97-A
Pages: 2518-2529
Related Report
Peer Reviewed
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