Fundamental Technologies for Bandwidth Compression Hardware to Overcome Memory-Wall Problem
| Project/Area Number |
26540017
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | Tohoku University |
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Principal Investigator |
Sano Kentaro 東北大学, 大学院・情報科学研究科, 准教授 (00323048)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2016: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2015: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2014: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
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| Keywords | バンド幅圧縮 / ハードウェア / 高性能計算 / FPGA / リコンフィギャラブル / 可逆データ圧縮 |
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| Outline of Final Research Achievements |
We developed technologies for bandwidth compression hardware that can be applied to numerical computing problems in order to address the memory-wall problem which degrades the computational performance. We have proposed a lossless data-compression algorithm based on prediction using continuity in numerical data and an encoding format to handle multiple data streams with compression. Then we have designed and implemented the bandwidth compression hardware by using FPGA. We built a high-performance stream computing system which performs fluid dynamics simulation with the lattice Boltzmann method with and without the bandwidth compression. We demonstrate that the system performs correct computation with bandwidth compression for DDR3 memories. We also made sure that the bandwidth compression actually enhances the sustained memory bandwidth for internal computing core, resulting in increasing performance by alleviating the memory bottleneck.
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Report
(4 results)
Research Products
(86 results)
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[Journal Article] ACM SIGARCH Computer Architecture News2014
Author(s)
Kentaro Sano, Ryotaro Chiba, Tomoya Ueno, Hayato Suzuki, Ryo Ito, and Satoru Yamamoto
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Journal Title
Proceedings of the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART)
Volume: 42(4)
Issue: 4
Pages: 45-50
DOI
Related Report
Peer Reviewed / Acknowledgement Compliant
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