| Project/Area Number |
63460134
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
YAJIMA Shuzo Faculty of Engineering, Kyoto Univ., Professor, 工学部, 教授 (20025901)
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| Co-Investigator(Kenkyū-buntansha) |
IWAMA Kazuo Faculty of Engineering, Kyoto Sangyo Univ., Assoc. Professor, 工学部, 助教授 (50131272)
OGINO Hiroyuki Faculty of Engineering, Kyoto Univ., Staff, 工学部, 教務職員 (40144323)
ISHIURA Nagisa Faculty of Engineering, Kyoto Univ., Instructor, 工学部, 助手 (60193265)
TAKAGI Naofumi Faculty of Engineering, Kyoto Univ., Instructor, 工学部, 助手 (10171422)
HIRAISHI Hiromi Faculty of Engineering, Kyoto Univ., Assoc. Professor, 工学部, 助教授 (40093299)
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| Project Period (FY) |
1988 – 1989
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| Project Status |
Completed (Fiscal Year 1989)
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| Budget Amount *help |
¥6,400,000 (Direct Cost: ¥6,400,000)
Fiscal Year 1989: ¥2,600,000 (Direct Cost: ¥2,600,000)
Fiscal Year 1988: ¥3,800,000 (Direct Cost: ¥3,800,000)
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| Keywords | Arithmetic Circuits / Hardware Algorithm / Fault-Tolerant Design / On-Line Error Detection / Logic Simulation / Fault Simulation / Test Generation / Redundant Coding / ハードウェアアルゴリズム / 論理シミュレーション / 故障シミュレーション |
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| Research Abstract |
We conducted researches for the design of highly reliable high-speed arithmetic circuits with redundant coding.
For (1) hardware algorithms for arithmetic operations with redundant coding and fault torelant design of circuits based on them and.(2) design verification of circuits and test generation, we got the following research results:
1. We designed an on-line error-detectable fast array divider based on a division algorithm with a redundant binary representation and a residue code which we had previously proposed.
2. We proposed a fast hardware algorithm for modular multiplication with a redundant representation. Modular multiplication with a large modulus is widely used in public key cryptosystems.
3. We clarified various properties of the redundancy of a redundant binary representation.
4. We proposed a time-symbolic simulation method as a new method for timing verification of logic circuits. We also implemented a simulator based on the method and a result analysis system.
5. We designed an algorithm for satisfiability problems of regular temporal logic, which we had proposed before for formal verification.
6. We presented a dynamic two-dimensional parallel method for fast fault simulation using a vector processor and implemented a fault simulator based on the method. We also presented a test pattern generation method using random patterns and implemented a program based on the method.
7. We showed an efficient method for locally exhaustive testing of combinational circuits using linear logic circuits.
We also researched on a method for generating prime implicants of logic functions, a representation method for logic functions and a hardware design language and got some results.
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