| 研究概要 |
Recently, multi-core design of VLSI systems becomes popular. Although current CMOS technology is capable of integrating enough transistors to realize multi-core system, the classic synchronous design method of VLSI systems leads to severe design challenges because of its bad flexibility. Therefore, the industry is giving serious consideration to the adoption of asynchronous design method to make full use of multi-core architecture. For example, Qualcomm announced multi-core Snapdragon S4 with their asynchronous SIM micro-architecture at MWC2012.
This research aims at asynchronous technology to develop high-efficiency asynchronous pipeline and asynchronous self-adaptive multi-voltage control scheme for multi-core VLSI systems. These two technologies would greatly improve the performance of throughput and power consumption. There are two achievements :
First, an efficient asynchronous domino logic pipeline (APCDP) is developed. APCDP is constructed based on constructed critical data path. Dual-rail domino logic is used to construct a stable critical data path. Single-rail domino logic is applied in non-critieal data paths. A high-speed encoding converter is designed to bridge the connection between dual-rail logic and single-rail logic.
Second, an efficient self-adaptive multi-voltage control scheme is proposed for saving power in asynchronous FPGA. An efficient self-adaptive control is designed, which evaluates the non-critical paths on-line and autonomously assigns a low supply voltage to save power. In normal state, non-critical paths work at low voltage. In low speed state, all paths are assigned with low voltage to save more power.
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