| 研究実績の概要 |
1. Back biasing effect
Positive VB yields a significant increase in Ion and decrease in SS in a wide range of middle ID region in spite of the increase in Ioff. Negative VB is attributable to the suppressed tunneling current, resulting in lower SSmin. It is revealed that tunneling current, especially vertical tunneling can occur from Ge-source to back interface of sSi-channel and current can flow through the inversion layer formed near back interface of sSi-channel. This vertical tunneling current shows high drain on current than lateral tunneling current because of high tunneling efficiency and these vertically tunneled electrons make an n-source at beneath the Ge-source and near back interface of sSi channel. However, the sSi channel is mainly controlled by VG because of much thinner EOT of front gate insulators than that of BOX. Consequently, this positive VB-induced vertical tunneling is greatly promising to improve the performance of Ge/sSi TFETs and it can be effectively utilized for improving the TFET performance by applying the synchronized VB with VG in multi-gate structure such as Fin FET, nanowire and so on.
2. Drain engineering
It is experimentally confirmed that the modified drain doping concentration of 1018 cm-3 is suitable for further performance improvement.
3. EOT scaling
In this study the EOT was scaling from 2.5 nm to 1.5 nm by changing the gate dielectric material from Al2O3 to HfO2. It is found that higher on current is obtained in thinner EOT device. However, the leakage current increases in HfO2-device because of large Dit with Ge and Si.
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