| 配分額 *注記 |
4,680千円 (直接経費: 3,600千円、間接経費: 1,080千円)
2022年度: 2,340千円 (直接経費: 1,800千円、間接経費: 540千円)
2021年度: 2,340千円 (直接経費: 1,800千円、間接経費: 540千円)
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| 研究実績の概要 |
Regarding our progress in the fiscal year 2023, we are exploring methods to reduce the power consumption of devices by combining the error resilience characteristics of DNNs with the switching characteristics of non-volatile devices. Theoretically, we have clarified the relationship between the fault tolerance of DNNs and the switching current of non-volatile devices, and experimentally, we have demonstrated a technique to reduce power consumption without compromising the accuracy of DNNs by introducing random errors into low 8-bit DNN parameters. The experimental results show that by inverting a random 20% of the binary digits, we can reduce the power consumption by 5.63%, and by inverting 100% of the binary digits, we can save 34.84% of energy. Furthermore, by incorporating the error map of six practical STT-MRAM chips, which have a maximum error rate of 0.00868, into the low 8-bit parameters of DNNs, there is no impact on their accuracy under the switching current equivalent to a 100% switching probability (with a maximum loss of 0.00067). The average top-1 and top-5 accuracy decreases for MobileNet are respectively 0.000355, 0.00079, 0.000670, and 0.000310, which has only a minimal impact on their industrial applications.
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| 現在までの達成度 (区分) |
現在までの達成度 (区分)
3: やや遅れている
理由
One of the challenges we faced was the delay in receiving publication results for our preliminary findings. This waiting period has slightly impacted the project's progress and the ability to share our discoveries with the wider scientific community for feedback and collaboration. Furthermore, the duration required to prepare the experimental environments exceeded initial expectations. Challenges included sourcing specific hardware components, setting up hardware circuit simulations, and ensuring the experimental setup could accurately measure the impact on power consumption and performance.
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| 今後の研究の推進方策 |
In the next step, we will continue to investigate the relationship between power consumption in non-volatile devices and the error tolerance characteristics of neural networks. Specifically, we aim to explore effective mathematical models to verify how optimal error tolerance can significantly reduce the power consumption of non-volatile devices. Following theoretical analysis, we will validate the impact of reducing the current in non-volatile devices on the power consumption and performance of MTJ cells from the perspective of hardware circuit simulation.
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