| 研究課題/領域番号 |
22K12024
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| 研究種目 |
基盤研究(C)
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| 配分区分 | 基金 |
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| 応募区分 | 一般 |
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| 審査区分 |
小区分60070:情報セキュリティ関連
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| 研究機関 | 金沢大学 |
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研究代表者 |
Cheng ChenMou 金沢大学, 電子情報通信学系, 研究協力員 (10814840)
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| 研究期間 (年度) |
2022-04-01 – 2025-03-31
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| 研究課題ステータス |
交付 (2023年度)
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| 配分額 *注記 |
1,950千円 (直接経費: 1,500千円、間接経費: 450千円)
2024年度: 650千円 (直接経費: 500千円、間接経費: 150千円)
2023年度: 650千円 (直接経費: 500千円、間接経費: 150千円)
2022年度: 650千円 (直接経費: 500千円、間接経費: 150千円)
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| キーワード | Isogeny cryptography / Domain-specific language / Haskell |
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| 研究開始時の研究の概要 |
Cryptography is being threatened by the emergence of large quantum computers, which can instantly break almost all of today's public-key cryptosystems. Isogeny-based cryptography is believed to remain secure even under such quantum attack. It has extremely small public keys and ciphertexts but is computationally more expensive than its competitors. In this project, we explore alternative architectures of specialized hardware accelerators to speed up isogeny-based cryptography. We hope that our research will make isogeny-based cryptography a practically viable solution to post-quantum security.
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| 研究実績の概要 |
This report presents the current progress on the development of a domain-specific hardware accelerators in enhancing the performance of isogeny-based cryptography, a promising candidate in the realm of post-quantum cryptography (PQC). The advent of quantum computing poses significant challenges to current cryptographic schemes, necessitating the development of PQC algorithms resilient against quantum attacks. Isogeny-based cryptography emerges as a compelling solution, offering smaller key sizes and ciphertexts. However, its practicality is hindered by inherent computational slowness. With the deceleration of Moore's Law, there's an urgent need for alternative strategies to enhance computational speed. This project investigates whether the perceived slowness of isogeny-based cryptography is inherent and explores hardware acceleration as a viable solution to this challenge. We have created a small yet powerful DSL embedded in Haskell to streamline the development of isogeny-based cryptosystems and their transformation into optimized hardware implementations. In particular, we highlight the emphasis on DSL design, compiler verification, and the application to isogeny-based cryptography. This year, we have completed the design of our DSL, embedded within Haskell and making heavy use of Haskell's features like dependent types for parametric design, as well as that of its extensive libraries.
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| 現在までの達成度 (区分) |
現在までの達成度 (区分)
3: やや遅れている
理由
We outline the progress and findings of a research project aimed at accelerating isogeny-based cryptography through a specialized, Haskell-embedded domain-specific language (DSL). Focusing on the balance between compactness and expressiveness, the project leverages Haskell's rich library ecosystem and advanced features like dependent types to enable efficient development, testing, and implementation of cryptographic systems on both software and hardware platforms. Also, because SIKE has been broken, we use CSIDH instead as our benchmarking application for our DSL, which we are currently close to the completion of its implementation and will soon move to testing and actual benchmarking. However, this is a bit behind the planned schedule, in which we should have moved to compiler construction and verification by now. This delay is largely caused by the fact that we are unable to recruit a qualified research assistant to work on this research project. We hope to be able to speed up the progress in the next year when we recruit a qualified and suitable research assistant.
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| 今後の研究の推進方策 |
Building on the comprehensive background and the progress made so far, the plan for future work on accelerating isogeny-based cryptography with a domain-specific hardware accelerator and DSL embedded in Haskell can be structured around several key objectives and strategies: (1) Design and implement a compiler that can transform DSL source code into both software (for debugging and testing) and efficient hardware instantiations, with a particular focus on generating zero-overhead implementations; (2) Integrate support for fully parameterized designs, enabling the compiler to adapt the hardware generation process to a wide range of applications; (3) Develop a verification methodology for the compiler, ensuring that it correctly translates DSL code into hardware and software implementations without errors; (4) Use the Haskell embedded DSL and the precise semantics framework as a basis for formal verification processes, possibly employing tools like Agda for mathematical proof of correctness; (5) Extend the framework to implement additional isogeny-based cryptosystems beyond CSIDH, leveraging the DSL to abstract the complexities of these systems; (6) Apply domain-specific optimizations identified during the DSL and compiler development phases, aiming to enhance performance and reduce computational costs in line with the target cost models; (7) Validate the scalability of the approach across different application scenarios, from datacenter servers to embedded systems, ensuring that the hardware accelerator meets the diverse needs of these environments.
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