| 研究課題/領域番号 |
23K13361
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| 研究種目 |
若手研究
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| 配分区分 | 基金 |
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| 審査区分 |
小区分21050:電気電子材料工学関連
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| 研究機関 | 千葉大学 |
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研究代表者 |
柯 夢南 千葉大学, 大学院工学研究院, 助教 (40849402)
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| 研究期間 (年度) |
2023-04-01 – 2025-03-31
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| 研究課題ステータス |
交付 (2023年度)
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| 配分額 *注記 |
4,680千円 (直接経費: 3,600千円、間接経費: 1,080千円)
2024年度: 1,950千円 (直接経費: 1,500千円、間接経費: 450千円)
2023年度: 2,730千円 (直接経費: 2,100千円、間接経費: 630千円)
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| キーワード | 半導体デバイス / トンネル効果 / トランジスタ / ゲルマニウム / 二次元材料 / MOS界面 |
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| 研究開始時の研究の概要 |
AI・IoT技術の発展により更なる低電圧・低消費電力FET技術が求められており、中でも急峻なサブスレッショルドスイング（S値）が得られるバンド間トンネルトランジスタ（TFET）の実用化が期待されている。しかし、妥当な性能を達成するため、オン電流の増加や十分広いゲート電圧範囲でのS値の低減など、実用化まで喫緊の課題となっている。本研究は、未来エレクトロニクス産業界の指針になるよう最先端高性能・高信頼性Ge/MoX2 TFETの創出を目指す。
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| 研究実績の概要 |
With the advancement of AI and IoT technologies, there is a growing demand for further low-voltage and low-power FET technology. Among these, the practical implementation of tunnel field-effect transistors (TFETs) with steep subthreshold slope (SS) values is highly anticipated. However, to achieve reasonable performance, there remain urgent challenges, such as increasing the on-current and reducing the SS over a sufficiently wide gate voltage range. This research aims to realize TFETs using heterostructures of two-dimensional materials like MoTe2 and MoS2 with three-dimensional materials such as Si and Ge. Furthermore, it aims to evaluate and improve these characteristics to create better-performing TFETs. The study focuses on three main aspects: the source material, the channel material, and the MOS interface, successfully establishing the foundational technology for vertical Ge/TMDC TFETs. Currently, the p-TFET has a maximum on/off ratio of approximately 2 orders of magnitude and a minimum SS of about 2100 mV/decade, the n-TFET has an on/off ratio of about 4 orders of magnitude and a minimum SS of about 560 mV/decade, indicating that there is still significant room for improvement in its characteristics.
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| 現在までの達成度 (区分) |
現在までの達成度 (区分)
2: おおむね順調に進展している
理由
This research aimed to realize vertical p-TFET and vertical n-TFET using heterostructures of MoTe2 and three-dimensional materials, and to evaluate and improve their characteristics to develop better-performing TFETs. Using MoTe2 and 3D material heterostructures for TFETs is a novel approach. The results of this study suggest that MoTe2 could become a new channel material option for practical TFET applications. Similarly, TFETs using Ge/MoS2 and Si/MoTe2 heterostructures were also fabricated. Comparative analysis showed that when Ge is used as the source material, the Ge/MoS2 TFET tends to have higher off-currents compared to Ge/MoTe2, resulting in reduced performance. Additionally, when Si is used as the source material, Ge/MoTe2 was found to achieve higher on-currents at lower drain voltages. This is likely due to the smaller bandgap of Ge compared to Si. The results of this study indicate that the Ge/MoTe2 heterostructure could be a promising source and channel material option for the practical implementation of TFETs.
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| 今後の研究の推進方策 |
To further enhance the performance of TFETs, many unresolved issues need to be addressed. In particular, it is necessary to develop a more effective gate. So far, h-BN has been used as the gate insulating layer, but because h-BN is a low-k material, the equivalent oxide thickness (EOT) of the gate becomes thicker, leading to reduced gate control capability and adversely affecting the SS.
To reduce the EOT of the gate structure, we plan to use Atomic Layer Deposition (ALD) to grow high-k materials such as aluminum oxide or hafnium oxide. At the same time, materials like graphene will be inserted to reduce contact resistance.
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