-
[文献書誌] M.Hanagata,Y.Horio and K.Aihara: "Asynchronous pulse neural network model for VLSI implementation" Trans.on Fundamentals,IEICE. E81A,9. 1853-1859 (1998)
-
[文献書誌] Y.Horio: "Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions" Report of the Research Institute for Technology,Tokyo Denki University. 9,1. 1-2.1-1-2.11 (1999)
-
[文献書誌] 当麻喜弘,三谷政昭,斉藤剛,稲葉博,堀尾喜彦,簑原隆: "ニューロ素子の高機能化とニューラルネットワークの高次処理に関する研究" 東京電機大学総合研究所年報. 17. 147-156 (1998)
-
[文献書誌] 花形満,堀尾喜彦,合原一幸: "VLSI化を目的とした非同期パルスニューラルネットワークモデル" 電子情報通信学会技術報告. NLP97,530. 29-35 (1998)
-
[文献書誌] Y.Horio,K.Yasuda,M.Hanagata and K.Aihara: "An asynchronous pulse neural network model and its analog IC implementation" Proc.Int.Conf.on Electronics,Circuits and Systems. 3. 301-304 (1998)
-
[文献書誌] Y.Horio,M.Hanagata and K.Yasuda: "An asynchronous pulse neural network model and its analog circuit implementation" Proc.Int.Symp.on Artificial Life and Robotics. 2. 336-341 (1998)
-
[文献書誌] 渡来賢一,堀尾喜彦: "連続時間遅延を持つ軸策回路の一構成法" 電子情報通信学会全国大会論文集. 1. 22 (1998)
-
[文献書誌] 安田和秀,花形満,堀尾喜彦: "非同期パルスニューロンモデルの集積回路化" 電子情報通信学会全国大会論文集. 1. 65 (1998)
-
[文献書誌] K.Yasuda,M.Hanagata R.Kasahara and Y.Horio: "Analog circuit implementation of asynchronous pulse neural network model" Proc.Int.Symp.on Nonlinear Theory and Its Applications. 2. 853-856 (1997)
-
[文献書誌] M.Hanagata and Y.Horio: "A modified asynchronous pulse neural network model for VLSI implementation" Proc.Int.Symp.on Nonlinear Theory and Its Applications. 2. 849-852 (1997)
-
[文献書誌] M.Hanagata and Y.Horio: "An asynchronous pulse neural network model with finite pulse width for VLSI implementation" Proc.Int.Conf.on Neural Information Processing and Intelligent Information Processing and Intelligent Information Systems. 1. 26-29 (1997)
-
[文献書誌] M.Hanagata and Y.Horio: "A modified asynchronous chaos neural network model for VLSI implementation" Proc.Int.Symp.on Circuits and Systems. 1. 657-661 (1997)
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[文献書誌] 堀尾 喜彦: "カオスニューロコンピュータ" Computer Today. 14,5. 14-21 (1997)