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[文献書誌] 堀井崇史: "処理要素間配線数の最小化に着目したロジックインメモリ VLSI システムのハイレベルシンセシス"電子情報通信学会春季全国大会予稿集. A-3-5. 109 (1999)
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[文献書誌] 帰山隼一: "ロジックインメモリ構造に基づく最小距離パターンマッチング VLSI"電気関係学会東北支部連合大会予稿集. 2H14. 271 (1999)
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[文献書誌] S.Kaeriyama: "Design of Multiple-Valued Logic-in-Memory VLSI Based on Linear Summation"The First Korea-Japan Joint Symposium on Multiple-Valued Logic. 1. 211-218 (1999)
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[文献書誌] 堀井崇史: "モジュール間転送時間を考慮したロジックインメモリ VLSI システムのハイレベルシンセシス"第59回情報処理学会全国大会予稿集. 1H2. 13-14 (1999)
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[文献書誌] T.Hanyu: "Muitiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs"Proc. Of 29th IEEE International Symposium on Muitiple-Valued Logic. 29. 30-35 (1999)
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[文献書誌] T.Hanyu: "Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic"IEICE Trans. Electronics. E82-C・9. 1662-1668 (1999)
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[文献書誌] S.Kaeriyama: "Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic"Proc. Of 30th IEEE International Symposium on Muitiple-Valued Logic. (発表予定). (2000)
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[文献書誌] T.Hanyu: "DRAM-Cell-Based Multi-Valued Logic0in-Memory VLSI with charge Addition and charge storage"Proc. Of 30th IEEE International Symposium on Muitiple-Valued Logic. (発表予定). (2000)