| 研究課題/領域番号 |
16F16764
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| 研究機関 | 東京工業大学 |
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研究代表者 |
松岡 聡 東京工業大学, 学術国際情報センター, 教授 (20221583)
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| 研究分担者 |
PODOBAS ARTUR 東京工業大学, 学術国際情報センター, 外国人特別研究員
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| 研究期間 (年度) |
2016-11-07 – 2019-03-31
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| キーワード | FPGA |
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| 研究実績の概要 |
The first segment of FY2017 continued to scrutinize the limitations of existing approaches and how they map to existing FPGAs. Where the first four months focused on empirically quantify the performance of the models, this second segment dived deeper into explaining the performance obtained with the models and their (likely) anomalies. This included analyzing the data-path the models generated, their mapping onto the FPGA fabric in terms of DSP-block, Block-RAM and LUT usage as well as how well they manage (pipeline) the critical path. The second segment of FY2017 focused on addressing the limitation found in the first segment to develop the necessary software to transcend state of the art FPGA performance. Our developed methods were compared to existing methods and the results were disseminated in international conferences.
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| 現在までの達成度 (区分) |
現在までの達成度 (区分)
2: おおむね順調に進展している
理由
John Gustafson (affil: A*CRC) introduced an alternative floating point format (called POSIT), which aims to supersede the (three decade old) traditional IEEE-754 floating point. Parts of my work here at Tokyo Institute of Technology has been to develop a tool for automatically generating hardware for POSITs. Currently there is no available hardware implementation for POSITs, and as such, the hardware impliciations are unknown. Our results of using POSITs on FPGAs and OpenCL, which have been disseminated in international conferences since the project started, filled the knowledge-gap and showed how well POSITs run on FPGAs to bring more attention to our work at precisions and FPGAs here at Tokyo Institute of Technology.
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| 今後の研究の推進方策 |
The last 8 months will focus on forecasting the requirements of future FPGA architecture such that they map well with HPC applications. We will take advantage of earlier results to identify what is lacking in existing FPGA architecture in order to boost performance. The study will use the hardware generated in the previous months and map it onto several "hypothetical" FPGAs that are different from the commercially available ones. These hyopthetical FPGAs will have have different amount of DSP-blocks, LUTs and other -- potentially coarse-grained -- resources. A performance model will be created in order to predict the performance that will gained using these alternative FPGAs. The results will be disseminated in international conferences.
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