| 研究課題/領域番号 |
18K11284
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| 研究機関 | 有明工業高等専門学校 |
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研究代表者 |
Gauthier Lovic 有明工業高等専門学校, 創造工学科, 准教授 (90535717)
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| 研究分担者 |
石川 洋平 有明工業高等専門学校, 創造工学科, 准教授 (50435476)
白鳥 則郎 中央大学, 研究開発機構, 機構教授 (60111316)
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| 研究期間 (年度) |
2018-04-01 – 2022-03-31
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| キーワード | HDL / HW design / Translation / Evaluation |
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| 研究実績の概要 |
The goal of the research is to design a new hardware description language (HDL), named HDLRuby[1], aiming at improving the design productivity of hardware systems.
During the year, the design of the language has been completed for supported any kind of register transfer level description using the planned advanced paradigms for proficient design. It has been evaluated on the implementation of a generic neural network, and prove to required a quadratic decrease of required lines of code with the number of neurons compared to an equivalent design in Verilog HDL [2]. Tools for generating Verilog HDL and VHDL from HDLRuby descriptions has been added [3]. The VHDL generation proved to be advanced enough to synthesize the circuit of a processor down to the layout using the Alliance tool set. This 8-bit Harvard processor - we called MEI8 - has been implemented from scratch in HDLRuby using less than 256 lines of code.Finally and a few libraries have been added for an easy design of common components including final state machines and decoders and have been used for the design of the processor mentioned above.
Publications:
[1] HDLRuby, a new High Productivity Hardware Description Language
[2] 新しいハードウェア記述言語”HDLRuby”の 生産力の評価
[3] 新しいハードウェア記述言語”HDLRuby”を Verilogへ翻訳するバックエンド
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| 現在までの達成度 (区分) |
現在までの達成度 (区分)
2: おおむね順調に進展している
理由
The language and its translation tools have been designed as planned and we managed to publish 3 papers and get positive evaluation results.
The only part that have not been implemented is the simulation engine, but it has been set to pending on purpose because the generated VHDL or Verilog HDL code can actually be simulated very efficiently on existing free or commercial HW simulators. Instead of the simulation engine, efforts have been spent on the design of more complex examples than initially forecast, i.e., a full-fledge processor or a neural network.
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| 今後の研究の推進方策 |
Now that the basis of HDLRuby has been completed, we plan to first complete the evaluation of the language on standard designs. Especially, an FPGA implementation of the MEI8 processor is in debug phase. The next step this year is to include in HDLRuby support for reconfigurable possibilities.
On the IoT side, it is planned to evaluate the implementation of edge-side HW-SW AI applications using HDLRuby.
Regarding the promotion of HDLRuby, it is planned to add support of the QFlow HW design flow, used by venture semiconductor companies.
For the academic side, publication are planned for evaluating the design productivity improvements of HDLRuby compared to VHDL and Verilog HDL using code metrics and design time as estimators.
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| 次年度使用額が生じた理由 |
There was uncertainty about the price of one FPGA device that could be settled only at the very end of the fiscal year when it was not possible to make another purchase.
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