| 研究実績の概要 |
The goal of the research project was to design and promote HDLRuby, a new high productivity hardware description language targeting edge computing applications.
Toward that end, this language has been developed from a prototype to a full hardware design framework usable for designing digital circuits.
In details, We implemented several tools for processing HDLRuby descriptions including a compiler for generating synthesizable Verilog HDL and VHDL code and a hardware simulator. We also implemented a library of generic components including for instance generators for final state machines, decoders, and arbitrary functions, as well as extension for fixed point or linear algebra processing. These tools and the library have been validated with the design and implementation targeting IC or FPGA of several circuits, e.g., a processor or neural networks. The code of the HDLRuby framework is publicly available online as standard packages and as source code repository. The last year has been dedicated first to the increase of the performance of HDLRuby so that its compilation time becomes negligible compared to the whole synthesis time. Second, we deepened the evaluation of this framework by performing a design exploration of the implementation of a binarized neural network on various FPGA devices as well as its integration within a wireless environment.
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