| 研究課題/領域番号 |
18K18026
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| 研究機関 | 九州工業大学 |
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研究代表者 |
Holst Stefan 九州工業大学, 大学院情報工学研究院, 助教 (40710322)
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| 研究期間 (年度) |
2018-04-01 – 2020-03-31
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| キーワード | VLSI / Logic Diagnosis / GPU Computing / Failure Analysis |
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| 研究実績の概要 |
Two research objectives (RO1 and RO2) were planned for the first fiscal year of this project.
The GPU-accelerated small delay fault diagnosis approach (RO1) have been fully developed and significant progress have been made towards the transparency of logic diagnosis results (RO2).
Additional to the originally planned objectives, two related works have been or are to be published. (a) A new method was developed for applying test data and gathering test responses reliably in the face of potential IR-drop and clock skew issues in the test infrastructure. (b) A new testable soft-error tolerant latch was proposed. Soft-errors are usually tolerated using cell-internal redundancy, but this redundancy also masks production defects. A new latch was developed enables testing of cell-internal production defects without compromising soft-error tolerance. Both works are important for collecting reliable diagnosis data from the chip.
One paper has been published at an international conference and three work-in-progress talks have been given at domestic and international workshops. Three more proposals have been submitted to international conferences, one will be published, one will be presented as a poster, and one is currently under review.
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| 現在までの達成度 (区分) |
現在までの達成度 (区分)
2: おおむね順調に進展している
理由
The GPU-accelerated small delay fault diagnosis approach (RO1) have been fully developed and its results will be presented at an international conference. While the work on RO2 are still underway and to be submitted soon to international conferences, two works related to reliable diagnostic data collection have been accepted at international conferences. These works go beyond the original research plan for the first fiscal year of this project.
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| 今後の研究の推進方策 |
In FY 2019, RO2 will be finalized by proposing a new way to report logic diagnosis results that allows deeper insights into the nature of unknown defects. We will also study how to incorporate additional knowledge on defect statistics into the precision diagnosis process to improve its success rate. Finally, a diagnostic pattern generator will be developed that actively collects additional diagnostic data from the chip under diagnosis.
During the past year, a new collaboration was formed with a research group at University of Paderborn, Germany to explore a combination of small delay fault diagnosis with their pioneering faster-than-at-speed testing (FAST) approach. FAST is able to test previously hidden small-delay faults by using capture times faster than the nominal functional clock speed of the circuit under test. It is expected that this collaboration again leads to a series of publications with results going beyond the original plan of this project.
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| 次年度使用額が生じた理由 |
The expenditures for computing hardware have been slightly lower than expected due to market developments and no student assistant was required in this financial year. The surplus funds will help covering the next year’s travel expenses which are expected to increase due to the higher number of publications to be presented at international conferences in FY 2019.
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