| 研究課題/領域番号 |
19K12092
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| 研究機関 | 国立研究開発法人理化学研究所 |
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研究代表者 |
TAN Yiyu 国立研究開発法人理化学研究所, 計算科学研究センター, 研究員 (70743243)
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| 研究期間 (年度) |
2019-04-01 – 2022-03-31
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| キーワード | sound field rendering / FDTD / FPGA |
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| 研究実績の概要 |
This research investigates a hardware-accelerated real-time sound field rendering system for large-scale sound spaces by co-designing algorithm and architecture. During the first year, the following works were studied.
Aim 1: new hardware-oriented and low-dispersion rendering algorithm to reduce computations and memory demands. Aim 2.1 system decomposition and parallelism. The research results are shown as follows.
Aim 1: The FDTD algorithm was analyzed, and a high-order FDTD method was developed to reduce the grid mesh dimension and memory requirement by applying the high-order approximation in the spatial domain and second-order approximation in the time domain. The numerical stability was analyzed, and the reflective boundary was derived. The high-order FDTD method only introduced the neighbor grids along the axes to update the sound pressure of a grid. Among the 6th-order, 4th-order, and 2nd-order schemes, the 6th-order scheme achieved the highest computation performance and the 2nd-order scheme obtained the fastest update speed of the grid mesh.
Aim 2.1: The system decomposition methods were compared and studied. The spatial parallelism was proposed to speed up computation and save required memory bandwidth, in which a sound space was divided into sub-sound-spaces, and a sliding window-based data buffering system was applied to alleviate external memory bandwidth bottlenecks. An FPGA-based accelerator with the 2nd FDTD scheme was developed to verify the proposed parallelism. It outperformed the software simulation on a desktop machine in computation performance.
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| 現在までの達成度 (区分) |
現在までの達成度 (区分)
2: おおむね順調に進展している
理由
According to the schedule, the hardware-oriented and low-dispersion rendering algorithm and the system decomposition method will be investigated in the first fiscal year. As described in the research outcome, a high-order FDTD scheme was developed, analyzed, and evaluated. Its performance was compared with other schemes. Furthermore, the system decomposition method and the spatial parallelism were researched, and an FPGA-based accelerator was developed to verify the proposed system decomposition and parallelism. The evaluation results showed it outperformed the software simulation on a desktop machine with much larger external memory and running at much higher clock frequency. The related results of the proposed algorithm and parallelism approach have already presented on international conferences. All these will benefit the development of the prototype system in the coming fiscal year. Based on the above, the project is progressed smoothly as our expected.
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| 今後の研究の推進方策 |
During the first year, the investigation of the rendering algorithm and system parallelism was finished. In the coming year, the development of the prototype machine will be focused on. The prototype machine will be developed to verify the proposed rendering algorithm and parallelism, evaluate performance, and compare with other solutions based on multi-core CPUs and GPUs. Additionally, system optimization approaches will also be investigated to improve the performance of the prototype machine.
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| 次年度使用額が生じた理由 |
Two main reasons lead to the remaining budget. (1) the instrument became cheaper when it was bought; and (2) another external fund was acquired to support the business trips to present research works. The remaining budget will be used to attend conferences to present our research works in the coming fiscal year. Additionally, it will also be consumed to buy some required consumable equipment for debugging the prototype machine.
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