| 研究課題/領域番号 |
19K12092
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| 研究機関 | 国立研究開発法人理化学研究所 |
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研究代表者 |
TAN Yiyu 国立研究開発法人理化学研究所, 計算科学研究センター, 研究員 (70743243)
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| 研究期間 (年度) |
2019-04-01 – 2022-03-31
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| キーワード | Sound Rendering / FDTD / FPGA |
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| 研究実績の概要 |
This research investigates a hardware-accelerated real-time sound field rendering system for large-scale sound space by co-designing algorithm and architecture. During the second year, novel hardware-accelerated system was developed to speed up computation. More details and research results are shown as follows.
(1)system specification and verification. Based on the high-order FDTD method and system decomposition method developed in last year, system data flow was analyzed and system architecture was specified, in which spatial blocking and temporal blocking were applied to reduce data accesses to external memory. A simulator was developed using C programming language to verify system functions and locate the performance bottleneck.
(2)development and evaluation of prototype machine. A prototype machine was designed using OpenCL programming language and implemented using the FPGA card DE10-Pro. The performance of the prototype machine, such as hardware resource utilization, computation time, computational throughput, was evaluated. Compared with the software simulation performed on a desktop machine with a Xeon Gold 6212U processor running at 2.4 GHz, the FPGA-based prototype machine achieved performance gain by 11 times, 13 times, and 18 times in the case of the 2nd-order, 4th-order, and 6th-order FDTD schemes, respectively, even though the prototype machine ran at much lower clock frequency and had much smaller on-chip memory.
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| 現在までの達成度 (区分) |
現在までの達成度 (区分)
2: おおむね順調に進展している
理由
According to the schedule, a hardware-accelerated system based on the proposed rendering algorithm will be developed to speed up computation and evaluated in the second fiscal year. As described in the research outcome, FPGA-based prototype machines with the 2nd, 4th, and 6th FDTD schemes were developed and evaluated. The evaluation results showed it outperformed the software simulation carried out in a desktop machine running at much higher clock frequency and containing much bigger on-chip memory. The related results have already presented in international conferences, and submitted to international academic journals. Based on the above, the project is progressed smoothly as what we expected.
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| 今後の研究の推進方策 |
During the first and second years, the rendering algorithm, system parallelism methods, and hardware prototype machine were studied. In the final year, the optimization of the prototype machine will be conducted to further improve computation performance, and a virtual concert hall will be developed to evaluate the real performance of the proposed acceleration system, including impulse response, sampling rate of the rendered results. In addition, the potential of extending the developed system to solve wave propagation problems in other application domains will be explored.
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| 次年度使用額が生じた理由 |
The main reason leads to the remaining budget is the pandemic of the COVID-19 virus, which results in the cancelling of business trip. In addition, we got the donation of the FPGA cards and related EDA design tools from Intel. Therefore, the budget of business trip and the cost to buy the experimental hardware and software license were saved. The remaining budget will be used to upgrade the simulation platform, attend conferences to present our research works, pay the publication fee, and buying the required consumable equipment for system debugging in the coming fiscal year.
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