| 研究実績の概要 |
Throughout this work, we have developed a versatile CAD-assisted circuit design platform and performance estimation tools for designing JTWPAs in different variants, which can reproduce the results of implemented JTWPAs in literatures.
In fabrication, we have been searching for the most suitable Josephson junction design to achieve a high homogeneity in Josephson junction parameters. From the beginning to end of the work, we have reduced the standard deviation (stdev) in junction resistance from over 20% down to 4% in our last measured sample, covering a chip area sufficient for implementing JTWPAs. Our latest junction design to be used in the next batch of JTWPA samples will further reduce the stdev to around 1%, while also greatly improving the junction yield over the previous designs.
From our sample measurements, we have successfully fabricated a low-loss nonlinear transmission line which could act as the basis for JTWPAs. With a comparable electrical length and number of unit cells to JTWPAs in literatures (1413 cells in our sample, comparing to 1000-2000 cells in literatures), we have achieved < 1dB insertion loss comparing to typically 3-6 dB in most other implementations over a similar frequency range. The preliminary measurement results of our samples demonstrated a gain up to an average of 7.5 dB, over a wide bandwidth of 6 GHz. We expect future devices to catch up in terms of gain with more optimized junction and circuit designs.
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