| Co-Investigator(Kenkyū-buntansha) |
MASU Kazuya Tohoku Univ., Res.Inst.Elect.Commun., Associated Professor, 電気通信研究所, 助教授 (20157192)
TSUBOUCHI Kazuo Tohoku Univ., Res.Inst.Elect.Commun., Professor, 電気通信研究所, 教授 (30006283)
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| Research Abstract |
In sub-0.1um MOSFETs, interconnect parasitics are drastically limiting the performance improvement. MOSFETs with wide gate width are essentially required for an application to high current-drivability devices such as word-line drivers, gate array devices and analog RF devices. In this work, in order to reduce the parasitic resistances, fully-self-aligned-metallization (FSAM) MOSFET using conventional salicide and selective Al-CVD techniques are proposed and investigated.
FSAM technology features ; (1) low contact resistivity of TiSi_2/Si, (2) self-aligned barrier layer formed by plasma nitridation of TiSi_2 surface, and (3) low sheet resistance of CVD-Al layer. At first, we have developed a self-aligned barrier layer formation method using N2 plasma nitridation of conventional silicided surface. It is confirmed that the 10-nm nitrided barrier layer is Ti-Si-N ternary amorphous layer. Furthermore, it is found that the Ti-Si-N layer acts as a diffusion barrier even after the 450ﾟC thermal treatment.
On the self-aligned barrier layer, aluminum films are successfully deposited in the same process chamber without breaking the vacuum. It is found that the aluminum films are selectively deposited on the conductive barrier layer.
For an application to analog RF-CMOS, high-frequency performance of wide-gate FSAM MOSFETs has been evaluated using RF simulation. Simulation results have shown that a transition frequency f_T of FSAM devices increases even below 0.2um gate length, while that of conventional silicide devices decrease with shrinkage of gate length down to 0.2um because of high parasitic resistances.
Furthermore, circuit design of RF-CMOS power amplifier for mobile phone has been investigated, and GHz-band high-efficiency CMOS push-pull amplifier has been proposed.
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