2013 Fiscal Year Annual Research Report
低消費電力マルチコアプロセッサとその並列ソフトウェアに関する研究
| Project/Area Number |
12F02730
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| Research Institution | Waseda University |
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Principal Investigator |
笠原 博徳 早稲田大学, 理工学術院, 教授
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| Co-Investigator(Kenkyū-buntansha) |
HILLENBRAND Dominic 早稲田大学, 理工学術院, 外国人特別研究員
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| Keywords | マルチコア / OS / コンパイラ / 低消費電力 |
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| Research Abstract |
The research lead to new results in the area of power control for mobile devices and for (cloud) servers which are found in data centers. On the Linux- and Android-operating system the run-time of OSCAR-compiled applications has been improved and also became more predictable. In order to achieve this success the operating system was modified to support more deterministic task to processor mappings. Furthermore the operating system was extended with a new programming interface (API) to control the performance of the processor cores. The API includes operations for dynamic frequency and voltage scaling (DVFS), clock- and power-gating. To assess the performance the operating system also collects data on CPU- and DRAM power consumption as well as processor temperature. The measurement setup performs fully automatic data acquisition. This allowed thousands of measurements to be collected over a month. The data was used to perform an offline design space exploration for a multi-core compiler run-time ("libgomp") and a scientific application. As a result the power consumption could be reduced without any modifications to the binary code of the application.
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
インテルやARMプロセッサマルチコアに対する消費電力削減制御を研究し、コンパイラランタイム、あるいはオペレーティングシステムを修正し、高速にクロックゲーティング等を実現できる環境を構築した。一部は既に国際会議等で発表している。
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| Strategy for Future Research Activity |
Currently the developed low-latency power control affects the application processors in system-on-chips (SoCs). However, in some SoCs a significant part of power consumption can be attributed to memory both on and off-chip - and to accelerators most - prominently GPUs. Since the power budget of mobile SoCs is in the range of a few Watts ca. 2-5W- but new SoCs will actually consume up to ca. 15 Watts. To keep within the thermal power budget the power consumed in the different subsystems must be carefully balanced and limited. Therefore the current framework of CPU power consumption will be extended to allow deeper research in this direction. This research will be significant for the Japanese semi-conductor business since this challenge applies to upcoming low-power (cloud) computer and mobile-systems.
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Research Products
(7 results)
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[Presentation] OSCAR Compiler Controlled Multicore Power Reduction on Android Pla tform2013
Author(s)
Hideo Yamamoto, Tomohiro Hira no, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Moriyuki Takamura, Keiji Kimura, and Hironori Kawahara
Organizer
The 26th International Workshop on Languages and Compilers for Parallel Computing, (LCPC2013)
Place of Presentation
Qualcomm Research Silicon Valley, USA
Year and Date
2013-09-26
Invited
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