| Research Abstract |
Although there are many hard computation problems. that have important applications, it is very difficult to solve large-scale problems. The purpose of this study is to investigate the custom circuit technology to accelerate hard computation problems. In particular, reconfigurable logic technology is extensively examined for an example application (subgraph isomorphism problem). Subgraph isomorphism problems are NP-complete, and two hardware algorithms have been proposed for the custom circuit design of this problem ; Ullmann's algorithm and Konishi's algorithm. We examined various implementations of these two algorithms, and found that the logic scales of these designs are too large for practical applications.
Generally, the logic scale of a logic circuit is reduced if some of its inputs are fixed to constant values. The derived circuit becomes smaller and faster than the original, while it is dependent on the input instances and thus not reusable. We call this kind of circuits as "data dependent circuits" in this study. With data dependent design, we can implement larger problems than its data "independent" version of hardware in the same logic scale. Reconfigurable logic devices are well suited for data dependent circuits, because they are reprogrammable at run-time One of the drawbacks of this approach is that we have to generate data dependent circuits for each input instances. Therefore, the total execution time of a data dependent circuit consists of the circuit generation time and the execution time. If the circuit generation time is much larger than the execution time, the circuit generation time may offset the acceleration by custom circuit. In this study, we designed, implemented, and evaluated the data dependent circuits for subgraph isomorphism problems, and showed that they are faster than the software even if the circuit generation time is included.
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