低消費電力デバイス向け化合物半導体と高誘電率絶縁膜及び金属電極の界面設計指針創出

2014 Fiscal Year Annual Research Report

• Project/Area Number: 13J08817
• Research Institution: Tokyo Institute of Technology
• Principal Investigator: ハサンザデ ダリューシュ 東京工業大学, 大学院総合理工学研究科, 特別研究員(PD)
• Keywords: Atomic layer deposition / La203 / InGaAs / MOSFET / Interface state traps / transconductance

Outline of Annual Research Achievements

This research focuses on understanding and engineering the interface at high-k and InGaAs for enabling low power, high performance devices for application in mobile devices. Rare metal earth oxide La203 is chosen as the high-k oxide in this research. The main issues facing high-k/InGaAs interface, is the formation of unstable oxides which lead to formation of several types of defects such as interface traps (Dit) and bulk traps within both the oxide and substrate. However, it was found that extremely low defect interfaces can be fabricated by using La203 due to formation of LaInGaO interfacial layer. This interfacial layer has an amorphous nature and prevents the formation of unstable oxides, thus improving the quality of the interface. Lowest reported Dit on smallest equivalent oxide thickness on InGaAs substrates in the order of lower 10 to the power of 11 was reported by atomic layer deposition(ALD) of La203 on InGaAs conducted in this research. Due to prevalence of finFET design in recent devices structures, it is important to evaluate the characteristics of La203 interface on various orientations of InGaAs substrate. Contrary to a planar device structure, the device channel region in a FinFET device is composed of multiple orientations. Therefore, it is important to achieve high quality interface on all substrate orientations in order to benefit from the superior electrostatic gate properties of the finFET designs. In this research, MOSFETs with ALD-deposited La203 oxide on [100], [110] and [111] oriented InGaAs substrates were fabricated. All p-type substrates used in MOSFETs had pre-formed source and drain regions. It was found that a similiar Dit can be achieved on all substrates. The substhreshold swing in all MOSFETs was ~130 mV/dec which imply similar interface characteristics. However, higher drain current and transconductance values were achieved for the substrate with [111] orientation. This effect could be related to lower effective mass of electrons in this surface which is a material property of crystalline surface. These resutls show the potential for using La203 in various InGaAs devices in idustry.

Research Progress Status

本研究課題は平成26年度が最終年度のため、記入しない。

Strategy for Future Research Activity

本研究課題は平成26年度が最終年度のため、記入しない。