2004 Fiscal Year Final Research Report Summary
A Psychologically-Inspired VLSI Brain Model System Implementing Subconscious Information Processing Based on Analog/Digital Marged Computation
| Project/Area Number |
14205043
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | The University of Tokyo |
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Principal Investigator |
SHIBATA Tadashi The University of Tokyo, Graduate School of Frontier Sciences, Professor, 大学院・新領域創成科学研究科, 教授 (00187402)
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| Co-Investigator(Kenkyū-buntansha) |
MITA Yoshio The University of Tokyo, School of Engineering, Lecturer, 大学院・工学系研究科, 講師 (40323472)
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| Project Period (FY) |
2002 – 2004
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| Keywords | Psychological Brain Model / VLSI System / Image recognition / Ferroelectric Memory / Hetero Gate Floating Gate MOS / DP Matching / Face Detection / Edge Filtering |
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| Research Abstract |
The purpose of this research is to develop a human-like flexible recognition system not by a sophisticated software processing but by developing VLSI hardware most efficiently mimicking the "human mind-processing".
The core of the system is the associative processor that autonomously recalls the maximum likelihood event in the past experience to a current input. We have developed an associative processor where the polarization in a ferroelectric film is utilized as the memory media in the system. In order to resolve the problem of depolarization in the film and the resultant degraded memory contents, a newly developed "Hetero-Gate Ferroelectric Floating Gate MOS" device was introduced to build associative circuitries. Experimental investigation on the ferroelectric film characteristics in such applications has been extensively conducted and it was shown that the system is most suited to such applications as mobile systems in which power dissipation is severely limited. ADP matching VLSI
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chip has been developed for episode memory recall. In episode memory, time sequences of events are stored and the most similar sequence needs be searched allowing some missing events or insertion of some extra events. This is a very computationally expensive processing. However, a very low-power and high-speed DP matching VLSI has been developed based on delay-encoding logic circuits. The system deals analog signals in the time domain while digital signals are utilized in the voltage domain, resulting in the fast and low power operation.
As a test vehicle of algorithm development, a face localization and verification system has been developed. Using the image feature vectors based on the edge information extracted from images, faces are very robustly detected from various scenes under different illumination, defocusing, scaling and rotation conditions. Since edge filtering is a very computationally expensive processing, various VLSI chips specialized for the processing have been developed and real-time response capability has been achieved. By operating the image vector generation VLSI at only 100MHz, it outperforms the software processing running on a PC having 2GHz CPU by a factor of approximately 10,000. Less
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Research Products
(70 results)
