2004 Fiscal Year Final Research Report Summary
Research of a High-speed Signal Transmission Scheme for Integrated Circuits
| Project/Area Number |
14350186
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
ONODERA Hidetoshi KYOTO UNIVERSITY, Department of Communications and Computer Engineering, Professor, 情報学研究科, 教授 (80160927)
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| Co-Investigator(Kenkyū-buntansha) |
KOBAYASHI Kazutoshi KYOTO UNIVERSITY, Department of Communications and Computer Engineering, Associate Professor, 情報学研究科, 助教授 (70252476)
HASHIMOTO Masanori Osaka University, Graduate School of Information Science & Technology, Associate Professor, 情報科学研究科, 助教授 (80335207)
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| Project Period (FY) |
2002 – 2004
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| Keywords | Signal Transmission / LSI / SerDes |
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| Research Abstract |
This research develops a design methodology to distribute GHz on chip high-speed signals to each portion of an LSI. The research topics are as follows.
・A technique to analyze characteristics of wires for high-speed signal transmission.
・A technique to analyze characteristics of power & ground-line structures.
・A design scheme of CMOS circuits for a high-speed signal transmission.
・Future performance predictions of on-chip high-speed signal transmission.
We first evlauate on-chip transmission-lines with orthogonal ground wires by real chip measurement. Conventionally, orthogonal ground wires are ignored in the discussion about resistance and inductance. However measurement results and results of field solvers show orthogonal ground wires are not negligible in high frequency over 10GHz. The characteristic of transmission-lines depends on frequency. However in circuit simulation, frequency-independent interconnect model is commonly used. Therefore the frequency used to model interconnects is
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one of the crucial problems. We develop a method to decide the single frequency based on the interconnect length. When we extract the interconnect characteristics, return current distribution strongly affects to the interconnect characteristics. We propose a method to select power/ground(p/g) wires that should be considered as return-path.
We discuss an IR-drop aware p/g grid design and develop a method to insert p/g straps. The proposed method targets the circuits operating at low frequency where the inductance of p/g wires are negligible. As the operating frequency becomes higher, the inductance of the p/g wires has significant effect to the p/g noise. We evaluate p/g noise with various structure of p/g net and various operating condition. Experimental results show when on-chip inductance become significant in p/g noise.
Current mode logic(CML) realizes on-chip high performance circuits. CML circuits can operate faster than conventional static CMOS logic circuits. We also develop a design method for high-speed multiplexer composed of CML and static CMOS. Designed multiplexers are verified by real chip measurement. Phase-Locked-Loop(PLL) is also important component in high-speed circuits. We analyze the performance trend of PLLs by improvement of the fabrication process.
Conclusively we evaluate the performance of whole signaling system includes transmission-line, driver circuit and receiver circuit. Less
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