2014 Fiscal Year Annual Research Report
低電圧動作シリコン系 Ｂｅｙｏｎｄ ＣＭＯＳデバイスの研究
| Project/Area Number |
14J09099
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| Research Institution | The University of Tokyo |
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Principal Investigator |
鄭 承旻 東京大学, 工学系研究科, 特別研究員(DC2)
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| Project Period (FY) |
2014-04-25 – 2016-03-31
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| Keywords | Low power CMOS / DIBL effect / Vth self-adjustment / Si nanowire |
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| Outline of Annual Research Achievements |
Recently, ultra-low power systems have attracted considerably for mobile applications. In order to realize ultra-low voltage operation, the advanced structure, materials or new mechanism for operation should be needed. Besides, the short channel effects also should be considered deeply. Meanwhile, DIBL is one of the short channel effects, which is still lack of research about device power consumption. Thus, in this study, the effect of DIBL is investigated in low power devices such as steep s transistor and subthreshold device. Furthermore, low voltage operation with new mechanism whose name is Vth self-adjusting MOSFETs is introduced and tri-gate nanowire transistor with floating gate which is enabling Vth self-adjustment is proposed to suppress short channel effects.
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| Current Status of Research Progress |
Current Status of Research Progress
1: Research has progressed more than it was originally planned.
Reason
The correlation between DIBL and CMOS power consumption was clearly established by simulation. Besides, the characteristics of tri-gate nanowire transistor with floating gate were analyzed using device simulation, especially its Vth self-adjustment characteristics. These simulation results will be based on fabrication of tri-gate transistor with floating gate.
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| Strategy for Future Research Activity |
The tri-gate nanowire transistor with floating gate will be demonstrated referring to simulation results. The transistors will be characterized about Vth self-adjustment which enables to improve on/off current ratio. Moreover, CMOS circuit will be simulated using measured parameter so that the advantages of the device will be verified about aspect of low power CMOS logic.
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