2015 Fiscal Year Annual Research Report
低電圧動作シリコン系 Ｂｅｙｏｎｄ ＣＭＯＳデバイスの研究
| Project/Area Number |
14J09099
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| Research Institution | The University of Tokyo |
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Principal Investigator |
鄭 承旻 東京大学, 工学系研究科, 特別研究員(DC2)
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| Project Period (FY) |
2014-04-25 – 2016-03-31
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| Keywords | Vth self-adjustment / Ultra-low Vdd operation / Nanowire MOSFET / SRAM stability |
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| Outline of Annual Research Achievements |
This study suggests a new operation mechanism, Vth self-adjustment, for sub-0.3 V operation even enhancing stability of SRAM cells. Vth self-adjusting MOSFETs show two kinds of Vth states in dynamic characteristics, while they show improved on/off current ratio and S-factor in static characteristics by time-lag of tunneling phenomenon. The Vth shift in dynamic characteristics can be used for enhancing stability of SRAM cells. Furthermore, improved on/off current ratio and S-factor are suitable for low voltage operation. However, Vth self-adjusting MOSFETs with planar structure show crucial short channel effects due to limitation of vertical scaling. Thus, gate-all-around (GAA) nanowire structure is introduced to Vth self-adjusting MOSFETs for strong immunity to short channel effects. In order to enhance Vth self-adjusting characteristics, the GAA nanowire structure is modified through enlarged body factor difference between dynamic and static characteristics. Hence, Vth shift and S-factor improvement become enhanced. Also, tri-gate nanowire MOSFETs with floating gates are successfully fabricated and they show excellent device performance. Finally, they show Vth self-adjusting characteristics even in ultra-low Vdd and these results are recomposed to 6 transistors (6T) SRAM cells using simulation. The 6T SRAM cells with Vth self-adjustment clearly show stability improvement at Vdd = 0.1 V.
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| Research Progress Status |
27年度が最終年度であるため、記入しない。
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| Strategy for Future Research Activity |
27年度が最終年度であるため、記入しない。
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