2007 Fiscal Year Final Research Report Summary
A 3 Dimensional Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains
Project/Area Number |
15106007
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Research Category |
Grant-in-Aid for Scientific Research (S)
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Allocation Type | Single-year Grants |
Research Field |
Communication/Network engineering
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Research Institution | Hiroshima University |
Principal Investigator |
IWATA Atsushi Hiroshima University, Graduate School of Advanced Sciences of Matter, Professor (30263734)
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Co-Investigator(Kenkyū-buntansha) |
MATTAUSH Hans Juregen Hiroshima University, Research Center for Nanodevices and Systems, Professor (20291487)
MIURA Mitiko Hiroshima University, Graduate School of Advanced Sciences of Matter, professor (70291482)
SASAKI Mamoru Hiroshima University, Graduate School of Advanced Sciences of Matter, Associate Professor (70235274)
KOIDE Tetsushi Hiroshima University, Research Center for Nanodevices and Systems, Associate Professor (30243596)
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Project Period (FY) |
2003 – 2007
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Keywords | wireless interconnection / inductor coupling / three dimensional integration / recognition systems / associative memory / pattern matching / learning function |
Research Abstract |
Research Objectives: 3D integration technologies using wireless interconnections and object recognition systems Research achievements: (1). Chip-to-chip wireless interconnection and 3D integration devices chip-to-chip wireless interconnection using electromagnetic induction between coupled inductors was proposed, and test circuits were designed and fabricated. Bit rate of 1Gb/s was achieved with 1mW power dissipation; Bit rate of 2.4Gb/s was achieved with high speed design. Three dimensional integration technology utilizing wireless interconnection using on-chip antenna and inductor coupled interconnection, named 3DCSS was proposed. Basic scheme and prototype systems were designed and fabricated. High performance image processing was realized with 3DCSS. Standing wave oscillator using inductor termination and coupling was proposed and a test chip was designed and fabricated with an 0.18um CMOS technology. 10GHz high quality oscillation signal with low phase noise was obtained. MOS device mod
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el (HiSIM) using surface potential was proposed, and highly accurate description capability with small number of parameters was effective for larger than 10GHz frequency range RF circuit applications. (2) Highly cognitive systems using chip-to-chip wireless interconnection An associative memory using analog and digital combined circuit techniques was developed, and highly speed operation with low power dissipation were confirmed. Highly functional, high performance pattern matching which was essential for detection, tracking and recognition of objects in image signals was implemented utilizing the associative memories. 3D prototype system integrating three kinds of image processing chips was implemented, and expected data transfer speed was obtained. Low voltage operated low noise amplifier and high performance VCO were also developed for basic circuit blocks. (3) Processing algorithm for implementing brain functions and systems Learning algorithm based on a human brain was implemented in an associative memory. By using the algorithm, a memory based learning model was proposed and its effectiveness for image recognition was confirmed. Less
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Research Products
(146 results)
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[Journal Article] Mixed Digital-Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search2007
Author(s)
M.A., Abedin, Y., Tanaka, A., Ahmadi, T., Koide, H.J., Mattausch
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Journal Title
Japanese Journal of Applied Physics (JJAP) Vol. 46, No. 4
Pages: 2231-2237
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories2007
Author(s)
M.A., Abedin, Y., Tanaka, A., Ahmadi, S., Sakakibara, T., Koide, H.J., Mattausch
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Journal Title
IEICE Trans. on Fundamentals Vol. E90-A, No. 5
Pages: 1240-1243
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Acceleration of DCT Processing with Massive-Parallel Memory-Embedded STME Matrix Prnrecsnr2007
Author(s)
T., Kumaki, K., Ishiraki T., Koide, H.J., Mattausch, Y., Kuroda, H., Noda, K., Dosaka, K., Arimoto, K., Saito
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Journal Title
IEICE Trans. on Information & Systems Vol. E90-D
Pages: 1312-1315
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Scalable FPGA/ASIC Implementation Architecture for Parallel Table-lookup Coding Using Multi-ported Content Addressable Memory2007
Author(s)
T., Kumaki, Y., Kono, M., Ishizaki, T., Koide, H.J., Mattausch
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Journal Title
IEICE Trans. on Information & Systems Vol. E90-D90, No. 1
Pages: 346-354
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Analysis of Technology Variations in Advanced MOSETs with the Surface-Potential-Based Compact Model HiSDII2007
Author(s)
K., Miura-Mattausch, N., Sadachika, K., Miyake, A., Yumisaki, H.J., Mattausch
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Journal Title
ECS Transactions Vol. 11, No. 6
Pages: 29-44
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Suface-Potential-Based Metal-Oxide Silicon-Varactor Model for RF Applications2007
Author(s)
M., Miyake, N., Sadachika, D., Navarro, Y., Mizukane, K., Matsumoto, T., Ezaki, M., Miura-Mattausch, et. al.
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Journal Title
Japanese Journal of Applied Physics Vol. 46, No. 4
Pages: 2091-2095
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Ontimizer2007
Author(s)
T., Kumaki, Y., Kuroda, M., Ishizaki, T., Koide, H.J., Mattausch, H., Noda, K., Dosaka, K., Arimoto, K., Saito
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Journal Title
IEICE Trans. on Information & Systems Vol. E90-D, No. 1
Pages: 334-345
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC2006
Author(s)
H. Noda, K., Dosaka, H.J., Mattausch, T., Koide, F., Morishita, K., Arimoto
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Journal Title
IEICE Trans. on Electronics Vol. E89-C
Pages: 1612-1619
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] HiSIM2CIRUIT SIMULATION2006
Author(s)
H.J., Mattausch, K., Miyake, T., Yoshida. S., Hazama, D., Navarro, N., Sadachika, T., Ezaki, M., Miura-Mattausch
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Journal Title
IEEE Circuits & Devices Magazine Vol. 22, No. 5
Pages: 29-38
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] HiSIM2 : Advanced MOSFET Model Valid for RF Circuit Simulation2006
Author(s)
M., Miura-Mattausch, N., Sadachika, D., Navarro, G., Suzuki, Y., Takeda, M., Miyake, T., Warabino, Y., Mizukane, R., Inagaki, T., Ezaki, H.J., Mattausch, et. al.
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Journal Title
IEEE Trans. on ELECTRON DEVICES Vol. 53, No. 9
Pages: 1994-2007
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] A carrier-Times-Delay-Based Nonquasi-Static MOSFET Model for Circuit Simulation and Its Application Harmonic Distortion Analysis2006
Author(s)
D., Navarro, Y., Takeda, M., Miyake, N., Nakayama, K., Machida, T., Ezaki, H.J., Mattausch, K., Miura-Mattausch
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Journal Title
IEEE Trans. on ELECTRON DEVICES Vol. 53, No. 9
Pages: 2025-2034
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] 20GHz, uniform-phase uniform-amplitude standing-wave Clock Distribution2006
Author(s)
M., Shiozaki, M., Sasaki, A., Mori, A., Iwata, H., Ikeda
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Journal Title
IEICE Electronics Express Vol. No. 3, No. 12
Pages: 11-16
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors2005
Author(s)
M., Shiozaki, T., Mukai, M., Ono, M., Sasaki, A., Iwata
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Journal Title
J. of Robotics and Mechatronics Vol. 17, No. 4
Pages: 463-468
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique2005
Author(s)
M., Shiozaki, T., Mukai, K., Ono, M., Sasaki, A., Iwata
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Journal Title
IEICE Trans. Electron Vol. E88-C, NO. 6
Pages: 1233-1240
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] A compact model of the pinch-off region of 100nm MOSFETs based on the surface-potential2005
Author(s)
D., Navarro, T., Mizoguchi, K., Suetake, K., Hisamitsu, H., Ueno, M., Miura-Mattausch, H.J., Mattausch, S., Ktunashiro, T., Ysmaguchi, K., Yamashita N., Nakayama
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Journal Title
IEICE Transactions on Electronics Vol. E88-C, NO. 5
Pages: 1079-1086
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] A Cost-Efficient High-Performance Dynamic TCAM with Pipelined Hierarchical Searching and Shift2005
Author(s)
H., Noda, K., Inoue, M., Kuroiwa, F., Igaue, K., Yamamoto, H.J., Mattausch, T., Koide, et. al.
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Journal Title
IEEE J. of Solid-State Circuits Vol. 40
Pages: 245-253
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] Non-quasi-static analysis with HiSIM,a complete surface-ootencial-based MOSFET model2005
Author(s)
T., Ezaki, Navarro, Y., Takeda, N., Sadachika, G., Suzuki, M., Miura-Matta usch, H.J., Mattausch
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Journal Title
MIXDES 2005 83-919289-9-3
Pages: 923-928
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] A Design of Wireless Neural-Sensing LSI2004
Author(s)
T., Yoshida, M., Akagi, T., Mashimo, A., Iwata, M., Yoshida,K., Uematsu
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Journal Title
IEICE Trans. Electronics Vol. E87-C, No. 6
Pages: 996-1002
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] A Design of Neural Signal Sensing LSI with Multi-Input Channels2004
Author(s)
T., Yoshida, T., Mashimo, K., Akagi, A., Iwata, M., Yoshida, K., Uematsu
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Journal Title
IEICE Trans. Fundamentals Vol. E87-A, No. 2
Pages: 376-383
Description
「研究成果報告書概要(欧文)」より
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[Journal Article] MOSFET Model HiSIM Based on Surface-Potential Description for Enabling Accurate RF-CMOS Design2004
Author(s)
M., Miura-Mattausch, H.J., Mattausch, T., Iizuka, K., Taguchi, S., Kumashiro, S., Miyamoto
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Journal Title
Journal of Semiconductor Technology and Science Vol. 4, No. 3
Pages: 133-140
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Hardware realization of two-stage pattern matching system using fully-parallel associative memories2007
Author(s)
M.A., Abedin, A., Ahmadi, Y., Tanaka, S., Sakakibara, T., Koide, H.J., Mattausch
Organizer
14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2007)
Place of Presentation
Hokkaido
Year and Date
2007-10-15
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Associative memory design realizing reference-pattern recognition and learning based on short/long-term storage concept2007
Author(s)
S., Sakakibara, M.A., Abedin, Y., Tanaka, A., Ahmadi, H.J., Mattausch, T., Koide
Organizer
14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2007)
Place of Presentation
Hokkaido
Year and Date
2007-10-15
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Acceleration of Advanced Encryption Standard (AES) processing on a CAM enhanced super parallel SIMD processor2007
Author(s)
M., Tagami, M., Ishizaki, T., Kumaki, Y., Kano, T., Koide, H.J., Mattausch, T., Gyohten, H., Noda, K., Dosaka, Arimoto, K., Saito
Organizer
14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2007)
Place of Presentation
Hokkaido
Year and Date
2007-10-15
Description
「研究成果報告書概要(欧文)」より
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[Presentation] PCA-based Object Detection/Recognition Chip for Wireless Interconnected 3-D Integration2007
Author(s)
H., Ando, S., Kameda, D., Arizona, N., Fuchigami, K., Kaya, M., Sasaki, A., Iwata
Organizer
2007 International Conference on Solid State Devices and Materials (SSDM)
Place of Presentation
Tsukuba
Year and Date
2007-09-21
Description
「研究成果報告書概要(欧文)」より
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[Presentation] A 0.6-Tbps, 16-port SRAM design with 2-stage-pipeline and multi-stage-sensing scheme2007
Author(s)
K., Johguchi, Y., Mukuda, K., Aoyama, H.J., Mattausch, T., Koide
Organizer
Proceedings of the 33rd European Solid-State Circuits Conference
Place of Presentation
Jarmany
Year and Date
2007-09-11
Description
「研究成果報告書概要(欧文)」より
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[Presentation] CAM enhanced super parallel SIMI) processor with high-speed pattern matching capability2007
Author(s)
T., Kumaki, Y., Kona, M., Ishizaki, M., Tagami, T., Koide, H.J., Mattausch, T., Gyohten, H., Noda, Y., Kuroda, K., Dosaka, K., Arimoto, K., Saito
Organizer
Proceedings of IEEE International MidWest Symposium on Circuits And Systems (MWSCAS2007)
Place of Presentation
CANADA
Year and Date
2007-08-05
Description
「研究成果報告書概要(欧文)」より
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[Presentation] On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Application2007
Author(s)
T., Sato, A., Inoue, T., Shiota, T., Inoue, Y., Kawabe, T., Hashimoto, T., Imamura, Y., Murasaka, M., Nagata, A., Iwata
Organizer
2007 IEEE ISSCC
Place of Presentation
San Francisco
Year and Date
2007-02-06
Description
「研究成果報告書概要(欧文)」より
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[Presentation] HiSIM231 : Toward Solving the Speed versus Accuracy Crisis in Circuit Simulation2007
Author(s)
H.J., Mattausch, N., Sadachika, M., Miyake, D., Navarro, T., Warabino, K., Matsumoto, T., Ezaki, M., Miura-Mattausch, et. al.
Organizer
The 4th International Workshop on Compact Modeling
Place of Presentation
Yokohama
Year and Date
2007-01-23
Description
「研究成果報告書概要(欧文)」より
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[Presentation] A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA2006
Author(s)
A., Ahmadi, M.A., Ritonga, M.A., Ahedin, H.J., Mattausch, T., Koide
Organizer
2006 IEEE Congress on Evolutionary Computation (WCCI2006)
Place of Presentation
Vancouver,Canada
Year and Date
2006-07-16
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Multi-Object Tracking VLSI Architecture using Image-Scan based Region Growing and Feature Matching2006
Author(s)
K., Yamaoka, T., Morimoto, H., Adachi, K., Awane, T., Koide, H.J., Mattausch
Organizer
2006 IEEE International Symposium on Circuits and Systems (ISCAS2006)
Year and Date
2006-05-21
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Adavanced Compact MOSFET Model HiSIM2 Based on Surface Potentials with Minimum Number of Approximation2006
Author(s)
K., Miura-Mattausch, D., Navarro, N., Sadachika, G., Suzuki, Y., Takeda, M., Miyake, T., Warabino, K., Machida, T., Ezaki, H.J., Mattausch, et. al.
Organizer
NSTI-Nanotech 2006
Place of Presentation
Boston. (invited)
Year and Date
2006-05-07
Description
「研究成果報告書概要(欧文)」より
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[Presentation] A 3D-Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains2005
Author(s)
A., Iwata, M., Sasaki, T., Kikkawa, S., Kameda, H., Ando, K., Kimoto, D., Arizono, H., Sunami
Organizer
IEEE 2005 ISSCC
Place of Presentation
San Francisco
Year and Date
20050206-10
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Substrate Integrity Beyond 1GHz2005
Author(s)
M., Nagata, M., Fukazawa, N., Hamanishi, M., Shiochi, T., Iida, J., Watanabe, Y., Murasaka, A., Iwata
Organizer
IEEE 2005 ISSCC
Place of Presentation
San Francisco
Year and Date
20050206-10
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Highly Parallel Huffman Encoding by Exploiting Multiple-Matches in Content Addressable Memory2005
Author(s)
Y., Kuroda, T., Kumaki, P., Koide, H.J., Mattausch, H., Noda, K., Dosaka, K., Arimoto, K., Saito
Organizer
Proceedings of the International SoC Design Conference (ISOCC2005)
Place of Presentation
Seoul, Korea
Year and Date
2005-10-21
Description
「研究成果報告書概要(欧文)」より
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[Presentation] Multi-Port CAM based VLSI Architecture for Huffman Coding with Real-time OptimizedCode Word Table2005
Author(s)
T., Kumaki, Y., Kuroda, T., Koide, H.J., Mattausch, H., Noda, K., Dosaka, K., Arimoto, K., Saito
Organizer
48th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2005)
Place of Presentation
Ohio USA
Year and Date
2005-08-07
Description
「研究成果報告書概要(欧文)」より
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[Presentation] CAM-based VLSI Architecture for Huffman Coding with Real-time Optimization of the Code Word Table2005
Author(s)
T., Kumaki, Y., Kuroda, T., Koide, H.J., Mattausch, H., Noda, K., Dosaka, K., Arimoto, K., Saito
Organizer
Proceedings of 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005)
Place of Presentation
Kobe
Year and Date
2005-05-24
Description
「研究成果報告書概要(欧文)」より
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[Presentation] MOSFET Modeling for RF-Circuit Simulation2004
Author(s)
M., Miura-Mattausch, H.J., Mattausch, T., Ohguro, T., Iizuka, M., Taguchi, S., Kumashiro, S., Miyamoto
Organizer
The 2004 Int. Conference on Solid-State and Integrated-CircuitTechnology
Place of Presentation
Beijing
Year and Date
2004-10-18
Description
「研究成果報告書概要(欧文)」より
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[Presentation] MOSFET Modeling for RF-Circuit Era2004
Author(s)
M., Miura-Mattausch, D., Navarro, Y., Takeda, H.J., Mattausch, T., Ohguro, T., Iizuka, M., Taguchi, S., Miyamoto
Organizer
The 11th International Conference on Mixed Design of Integrated Circuits and Systems 2004
Place of Presentation
Szczecin
Year and Date
2004-06-24
Description
「研究成果報告書概要(欧文)」より
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