2005 Fiscal Year Final Research Report Summary
Studies on Test Architecture for Test Data Compression / Decompression
| Project/Area Number |
15300021
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hiroshima City University |
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Principal Investigator |
ICHIHARA Hideyuki Hiroshima City University, Faculty of Information Sciences, Associate Professor, 情報科学部, 助教授 (50326427)
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| Co-Investigator(Kenkyū-buntansha) |
INOUE Tomoo Hiroshima City University, Faculty of Information Sciences, Professor, 情報科学部, 教授 (40252829)
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| Project Period (FY) |
2003 – 2005
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| Keywords | LSI testing / Data compression / Decompressor / Test data / Statistical coding / Test cost / Reconfigurability / Variable-length coding |
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| Research Abstract |
We researched test data compression and decompression schemes for VLSI testing in terms of usefulness.
In 2003, first, we analyzed a relationship between compression algorithms using variable-length codes and test application. Based on this analysis, we proposed a model of decompressors with buffer for applying compressed test data. This model can raise some limitations on test application. In addition, we proposed a test vector reordering algorithm to minimize the size of the buffer on the decompressor model. On the other hand, we proposed a response compression coding method based on Huffman coding. The proposed coding method guarantees zero-aliasing and it is independent of the fault model and the structure of a circuit-under-test.
In 2004, according to the above analysis, we proposed a new Huffman-based coding method for achieving small test application time in a given test environment. The proposed coding method adjusts both of the compression ratio and the length of the cord words to the test environment. We also proposed a cost-effective test generation method for highly compressible test data while keeping the number of generated test sets small. Moreover, we began to discuss flexibility of decompressors using reconfigurable VLSI.
In 2005, we developed the last year's discussion, and introduced an embedded decompressor that is reconfigurable according to the used coding algorithms and a given test data. Its reconfigurability can overcome the drawbacks of conventional decompressors with keeping high compression ratio. Moreover, we propose an architecture of reconfigurable decompressors for four variable-length codings. In the proposed architecture, the common functions for four codings are implemented as fixed (or non-reconfigurable) components so as to reduce the configuration data, which is stored on an ATE and sent to a CUT.
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Research Products
(13 results)
