Design Guideline for High-Performance Si Nano-wire Transistor by Optimization of Thermal and Impurity Properties

2017 Fiscal Year Final Research Report

• Project/Area Number: 15H03997
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Keio University
• Principal Investigator: Uchida Ken 慶應義塾大学, 理工学部(矢上), 教授 (30446900)
• Project Period (FY): 2015-04-01 – 2018-03-31
• Keywords: ナノ構造 / 不純物 / イオン化エネルギー / 量子効果 / 誘電率 / 熱伝導率測定

Outline of Final Research Achievements

The properties of shallow impurities in nanoscale semiconductors were thoroughly evaluated and it is demonstrated that the ionization energy of shallow impurities is larger as the size of nanoscale semiconductors shrinks. In Si nanosheet, the enhancement of ionization energy and an increase in critical doping concentration were experimentally confirmed. In Si nanowire, the impurity level was numerically obtained. Furthermore, the characteristics of Si nanowire tunneling FETs were investigated with respect to the radial impurity position dependence. In addition, thermal conductivity of Al2O3 deposited by atomic-layer deposition technique was studied. It is shown that the thermal conductivity is enhanced by thermal annealing. The information of the thermal conductivity will be used to further enhance the performance of Si nanowire transistors.

Free Research Field

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