2015 Fiscal Year Annual Research Report
ＩＩＩ－Ｖ ＣＭＯＳフォトニクスを用いた光電子集積回路に関する研究
| Project/Area Number |
15J08956
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| Research Institution | The University of Tokyo |
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Principal Investigator |
朴 珍權 東京大学, 工学系研究科, 特別研究員(DC2)
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| Project Period (FY) |
2015-04-24 – 2017-03-31
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| Keywords | Direct wafer bonding / Monolithic integration / III-V on insulator / InGaAsP / Photonic device |
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| Outline of Annual Research Achievements |
By high temperature annealing, the bonded wafer shows severe void generation. These voids lead to the malfunction of photonic devices and process fail. Therefore, suppressing void generation on bonded wafer is necessary. The voids is originated from moisture in bonded layer (ALD-Al2O3). To suppress the void generation, we apply pre-bonding annealing method.
To achieve effective optical modulation, low resistivity P-I-N junction is necessary. However, conventional ion implantation method was difficult to achieve low resistance of PIN junction because of low dopant solubility of III-V material. The low dopant solubility need high temperature and long-time activation process. However, the high temperature annealing is not suitable for III-V on insulator wafer. To overcome this problem, we apply the Zn diffusion and Ni-InGaAsP alloy for p+ and n+ junction, respectively. Especially, we firstly demonstrated Ni-InGaAsP alloy to replace the Si ion implantation. The Ni-InGaAsP alloy was formed very low temperature under 350C and shows 100 times lower sheet and contact resistance compare to conventional Si ion implantation method.
Based on result, we applied it to InGaAsP photonic devices. By the Ni-InGaAsP and Zn diffusion method, we reduced the total process temperature under 500C to fabricate InGaAsP variable optical attenuator. The InGaAsP VOA shows a very large attenuation characteristic of -40dB/mm at 40mA/mm current injection. By a numerical analysis, we understand that this large attenuation comes from the intervalenceband absorption of InGaAsP material.
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
In previous year, we evaluate various process technology to find suitable process for our integrated switch. By these research, we found several problem to achieve final goal and try to solve this problem. Through the pre-bonding annealing process we successfully suppress the void generation of III-V on insulator wafer and achieve very low junction resistance using Ni-InGaAsP alloy and Zn diffusion method. Based on these results, we successfully fabricate the InGaAsP variable optical attenuator on III-V on insulator with very low process temperature and investigate the absorption characteristic. By these result, we have secured all of process technology for our integrated photonic switch.
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| Strategy for Future Research Activity |
In previous year, we secured all of process technology for our integrated device. Therefore, we try to integration between electronic and photonic devices on III-V on insulator substrate.
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