Design-for-testability circuit for detecting delay faults at interconnects in 3D stacked ICs

2017 Fiscal Year Final Research Report

• Project/Area Number: 15K00079
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: The University of Tokushima
• Principal Investigator: Yotsuyanagi Hiroyuki 徳島大学, 大学院社会産業理工学研究部(理工学域), 准教授 (90304550)
• Project Period (FY): 2015-04-01 – 2018-03-31
• Keywords: VLSIの検査技術 / 検査容易化設計 / ３次元積層チップ / 遅延故障 / LSIテスト / ディペンダブル・コンピューティング

Outline of Final Research Achievements

In this research, we propose design-for-testability circuits for testing delay fault occurred at interconnects in 3D stacked ICs. We also estimate the delay caused by defects in Through-Silicon-Via (TSV) or microbump used in interconnects using an electromagnetic simulator and a circuit simulator. The proposed design-for-testability circuit can detect delay faults by time-to-digital converter embedded in boundary scan design. The place and route method for reducing internal routing of TDC was also developed. We also fabricated some experimental ICs to evaluate delay gates which have small propagation delay variations and evaluate the feasibility of testing multiple TSVs simultaneously.

Free Research Field

計算機システム