2005 Fiscal Year Final Research Report Summary
Fundamental Study on Low-loss SiC Power Devices Using Multi pn Junctions
| Project/Area Number |
16360153
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
KIMOTO Tsunenobu Kyoto University, Department of Electronic Science and Engineering, Associate Professor, 工学研究科, 助教授 (80225078)
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| Co-Investigator(Kenkyū-buntansha) |
SUDA Jun Kyoto University, Department of Electronic Science and Engineering, Lecturer, 工学研究科, 講師 (00293887)
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| Project Period (FY) |
2004 – 2005
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| Keywords | Silicon Carbide / Power Device / MOSFET / Multi pn Junction / RESURF Structure / デバイスシミュレーション |
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| Research Abstract |
In this research project, designing and fabrication of low-loss, high-voltage silicon carbide (SiC) power devices with multi pn junction structures have been investigated. In the multi pn junction structures, two- or three-dimensional extension of space charge regions enables the usage of highly doped semiconductors, by which on-state resistance can be significantly reduced. This is the first investigation on SiC power devices with such structures. As a typical device, lateral high-voltage MOSFETs have been investigated.
Effects of doping concentration of each region on breakdown voltage and on-resistance of SiC RESURF (Reduced Surface Field) MOSFETs have been analyzed by using a two-dimensional device simulator. Effective charge at the MOS interface influences the space charge region and thereby breakdown voltage. Optimum dose designing and its guideline have been determined. Double RESURF structure with a pnp layer structure is effective to reduce on-resistance. The breakdown voltage can be increased because the electric field inside the oxide is reduced.
SiC Lateral RESURF MOSFETs have been fabricated on 10 μm-thick p-type epilayers. Ion implantation was employed to form RESURF, top-p, source, and drain regions. The gate oxide was grown by direct oxidation in N_3O at 1300℃. The typical channel length, RESURF length were 2〜3μm and 20μm, respectively. An original self-aigned process has been developed to fabricate double RESURF MOSFETs. A single-zone double RESURF MOSFET fabricated in this study exhibited a breakdown voltage of 750 V and a low on-resistance of 52 mΩcm^2. The original two-zone double RESURF MOSFET showed characteristics of 1380 V - 66mΩcm^2, which is the pest performance among any lateral MOSFETs ever reported.
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Research Products
(13 results)
