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2006 Fiscal Year Final Research Report Summary

Research for ultra-fast operation of InP HBT by ballistic transportation in collector

Research Project

Project/Area Number 16360170
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field Electron device/Electronic equipment
Research InstitutionTokyo Institute of Technology

Principal Investigator

MIYAMOTO Yasuyuki  Tokyo Institute of Technology, Department of Physical Electronics, Assoc.Prof., 大学院理工学研究科, 助教授 (40209953)

Co-Investigator(Kenkyū-buntansha) MACHIDA Nobuya  Tokyo Institute of Technology, Department of Physical Electronics, Assistant Prof., 大学院理工学研究科, 助手 (70313335)
Project Period (FY) 2004 – 2006
KeywordsHeterojunction bipolar transistor / InP / Electron beam lithography / Ballistic electron / Collector capacitance / Narrow emitter / Collector transit time / Kirk effect
Research Abstract

Obtained results in this study are as follows :
Electron velocity in the collector was estimated by Monte Carlo simulation. In the heterojunction bipolar transistor with 100 nm thick collector, electron velocity is over 4x10^7cm/s at first 40 nm, but the velocity is less than 2x10^7cm/s at final 20 nm. With base thickness of 25 nm, estimated cutoff frequency is about 630 GHz.
Thus we propose hot electron transistors with intrinsic semiconductor as propagation region for ballistic transportation and thermionic hetero-launcher for high drivability controlled by insulated gate. Electron speed in the collector is over 7x10^7cm/s and cutoff frequency over 1 THz is estimated when collector current density is over 1000 kA/cm^2.
Heterojunction bipolar transistors with 0.1um wide buried metal wires showed 0.6 fF as total collector capacitance. To our knowledge, this is the smallest capacitance. However, electron flux from side of the wire limits further improvement. Thus we proposed heterojunction bipolar transistors with SiO_2 wire under base contact region. 200-nm-thick wires were buried in heterojunction bipolar transistor structure with flat hetero-interface. In the transistors with SiO_2 wire, no serious degradation was observed in DC measurements. Hot electron transistors with insulated gate and thermionic hetero-launcher were fabricated. Good isolation of gate and collector current control by gate bias were confirmed.

  • Research Products

    (18 results)

All 2007 2006 2005 2004

All Journal Article (15 results) Patent(Industrial Property Rights) (3 results)

  • [Journal Article] InP buried growth of Si02 wires toward reduction of collector capacitance in HBT2007

    • Author(s)
      Y.Miyamoto
    • Journal Title

      J. Cryst, Growth 298

      Pages: 867-870

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Increase of collector current in hot electron transistors controlled by gate bias2007

    • Author(s)
      A.Suwa
    • Journal Title

      Jpn. J. Appl. Phys. 46・9

      Pages: L202-L204

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Numerical Analysis of the Effect of P-Regions on the I-V Kink in GaAs MESFETs2007

    • Author(s)
      K.Nishihori
    • Journal Title

      Trans. IECE of Japan E90-C(掲載決定(6号))

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] InP buried growth of Si02 wires toward reduction of collector capacitance in HBT2007

    • Author(s)
      Y.Miyamoto
    • Journal Title

      J.Cryst, Growth 298

      Pages: 867-870

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Increase of collector current in hot electron tran sistors controlled by gate bias2007

    • Author(s)
      A.Suwa
    • Journal Title

      Jpn.J.Appl.Phys. 46・9

      Pages: L202-L204

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Numerical Analysis of the Effect of P-Regions on the I-V Kink in GaAs MESFETs2007

    • Author(s)
      K.Nishihori
    • Journal Title

      Trans.IECE of Japan

      Pages: E90-C

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Current Gain and Voltage Gain in Hot Electron Transistors without Base Layer2006

    • Author(s)
      Yasuyuki MIYAMOTO
    • Journal Title

      Trans. IECE of Japan E89-C, 7

      Pages: 972-978

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Charging Time of Double-Layer Emitter in Heterojunction Bipolar Transistor Based on Transmission Formalism2006

    • Author(s)
      Nobuya Machida
    • Journal Title

      Jpn. J. Appl. Phys. 45・35

      Pages: L935-L937

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] MC simulation of ultrafast transistor using ballistic electron in intrinsic semiconductor and its fabrication feasibility2006

    • Author(s)
      K.Furuya
    • Journal Title

      Journal of Physics : Conference Series 38

      Pages: 208-211

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Current Gain and Voltage Gain in Hot Electron Transistors without Base Layer2006

    • Author(s)
      Yasuyuki MIYAMOTO
    • Journal Title

      Trans.IECE of Japan E89-C, 7

      Pages: 972-978

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Charging Time of Double-Layer Emitter in Heterojunction Bipolar Transistor Based on Transmission Formalism2006

    • Author(s)
      Nobuya Machida
    • Journal Title

      Jpn.J.Appl.Phys. 45・35

      Pages: L935-L937

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Double-Slit Interference Observation of Hot Electrons in Semiconductors-Analysis of Experimental Data-2005

    • Author(s)
      Kazuhito Furuya
    • Journal Title

      Jpn. J. Appl. Phys. 44

      Pages: 2936

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Double-Slit Interference Observation of Hot Electrons in Semiconductors--Analysis of Experimental Data-2005

    • Author(s)
      Kazuhito Furuya
    • Journal Title

      Jpn.J.Appl.Phys. 44

      Pages: 2936

    • Description
      「研究成果報告書概要(欧文)」より
  • [Journal Article] Impact of Latent Image Quality on Line Edge Roughness in Electron Beam Lithography2004

    • Author(s)
      Masaki Yoshizawa
    • Journal Title

      Jpn. J. Appl. Phys. 43・6B

      Pages: 3739

    • Description
      「研究成果報告書概要(和文)」より
  • [Journal Article] Impact of Latent Image Quality on Line Edge Roughness in Electron Beam Lithography2004

    • Author(s)
      Masaki Yoshizawa
    • Journal Title

      Jpn.J.Appl.Phys. 43・6B

      Pages: 3739

    • Description
      「研究成果報告書概要(欧文)」より
  • [Patent(Industrial Property Rights)] ホットエレクトロントランジスタ2005

    • Inventor(s)
      宮本, 古屋, 浅田, 町田
    • Industrial Property Rights Holder
      東工大
    • Industrial Property Number
      特願2005-334326
    • Filing Date
      2005-11-18
    • Description
      「研究成果報告書概要(和文)」より
  • [Patent(Industrial Property Rights)] バイポーラトランジスタ及びその製造方法2005

    • Inventor(s)
      宮本, 山本, 石田
    • Industrial Property Rights Holder
      JST
    • Industrial Property Number
      特願2005-334991
    • Filing Date
      2005-11-18
    • Description
      「研究成果報告書概要(和文)」より
  • [Patent(Industrial Property Rights)] 光信号送信装置及び光信号伝送システム2005

    • Inventor(s)
      宮本, 浅田
    • Industrial Property Rights Holder
      JST
    • Industrial Property Number
      特願2005-356694
    • Filing Date
      2005-12-09
    • Description
      「研究成果報告書概要(和文)」より

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Published: 2008-05-27  

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