2006 Fiscal Year Final Research Report Summary
A Study on Circuit-Specialization based on Reconfigurable Logic Devices
| Project/Area Number |
16500029
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | Toyohashi University of Technology |
|---|
Principal Investigator |
ICHIKAWA Shuichi Toyohashi University of Technology, Dept. Knowledge-based Information Engineering, Associate Professor, 工学部, 助教授 (70262855)
|
|---|
| Project Period (FY) |
2004 – 2006
|
| Keywords | FPGA / Reconfigurable logic circuit / Partial evaluation / Custom computing circuit / High-performance / Reduction of logic scale |
|---|
| Research Abstract |
Generally, the logic scale of a logic circuit is reduced if some of its inputs are fixed to constant values. The derived circuit becomes smaller and faster than the original, while it is dependent on the input instances and thus not reusable. This kind of technique is called "specialization" or "partial evaluation", which has originally been studied for software. Circuit-specialization is best suited to reconfigurable logic devices (e.g., FPGA), and its applications are not fully explored yet. The purpose of this study is to examine the applications and advantages of circuit-specialization based on reconfigurable logic devices.
The results of this study include the following items.
1. The design and evaluation of data-dependent hardware for Subgraph Isomorphism problem (IEICE Trans. ED, v.E87-D, pp.2038-2047).
2. Custom computing hardware for the 3x+1 problem (IEEE TENCON2004, v.D, pp.387-390), where circuit specialization is effective to improve performance/area ratio (Ann. Mtg. Rec. IEEJ 2005, v.3, pp.87-88).
3. Design and evaluation of data-dependent hardware for AES encryption algorithm (IEICE Trans. ED, v.E89-D, pp.2301-2305).
4. A method to convert a PLC instruction sequence into hardware description to generate a small and fast control circuit (IEEE ISIE2006, pp. 2930-2935).
5. Design and evaluation of hardware Pseudo-Random Number Generator MT19937 (IEICE Trans. ED, v.E88-D, pp. 2876-2879).
6. Redundancy in instruction sequences of computer programs (IEICE Trans. EA, v.E89-A, pp.219-221).
|
