Universal gate stack for 2D layered channel

2018 Fiscal Year Final Research Report

• Project/Area Number: 16H04343
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: The University of Tokyo
• Principal Investigator: Nagashio Kosuke 東京大学, 大学院工学系研究科(工学部), 准教授 (20373441)
• Project Period (FY): 2016-04-01 – 2019-03-31
• Keywords: ２次元層状材料 / トランジスタ / 絶縁膜堆積

Outline of Final Research Achievements

In this study, we have introduced differen-tial-pressure-type deposition chamber, in which the feed source and the deposition chambers are separated by small aperture and can be evacuated in-dependently. By controlling the deposition condition such as deposition rate, PO2 and temperature, the insulator properties are evaluated by the I-V measurement. We demonstrate the top gate capacitance of 1.14 uF/cm2 by analyzing the I-V data for dual-gate graphene FET.

Free Research Field

半導体デバイス工学

Academic Significance and Societal Importance of the Research Achievements

2次元層状材料は，電子デバイス展開が期待されるが，原子層物質であるがゆえ環境に特性が敏感であり，本来の特性を得ることが難しいという問題がある．本研究では，ゲートスタックにおいて最も重要な絶縁膜堆積において酸素分離型蒸着装置を用いた特性劣化の少ない手法を開発した．今後のデバイス作製プロセスにおいて重要な役割を担うことが期待される．