2018 Fiscal Year Annual Research Report
２次元半導体ＭｏＳ２トランジスタにおける界面特性の理解と制御
| Project/Area Number |
17J09690
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| Research Institution | The University of Tokyo |
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Principal Investigator |
方 楠 東京大学, 大学院工学系研究科, 特別研究員(DC2)
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| Project Period (FY) |
2017-04-26 – 2019-03-31
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| Keywords | MoS2 / interface / capacitance measurement / accumulation-mode FET |
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| Outline of Annual Research Achievements |
The understanding of operation mode as well as interface are important for 2D materials based FET. An accumulation-mode FET model is developed based on a partial top-gate MoS2 FET.
The operation mechanism of an accumulation-mode FET is validated and clarified by the capacitance measurement. A depletion capacitance－quantum capacitance transition is observed. The universal thickness scaling rule of 2D-FETs is then proposed, which provides guidance for future research on 2D materials.
The interface properties of MoS2 is systematically investigated. For conduction band side, interface states are mainly attributed to Mo-S bond bending caused by the surface strain and the substrate roughness. For valance band side, the interface states mainly come from the sulfur vacancy induced defect-states.
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| Research Progress Status |
平成30年度が最終年度であるため、記入しない。
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| Strategy for Future Research Activity |
平成30年度が最終年度であるため、記入しない。
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