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2008 Fiscal Year Annual Research Report

ナノスケール配線および回路のシグナル・インテグリティに関する研究

Research Project

Project/Area Number 18063008
Research InstitutionTokyo Institute of Technology

Principal Investigator

益 一哉  Tokyo Institute of Technology, 統合研究院, 教授 (20157192)

Keywordsナノ配線 / シグナル・インテグリティ / インテグリティ / 揺らぎ / ばらつき
Research Abstract

本研究では、加工寸法で言えば32nm以降のナノスケールデバイスやナノ配線を集積化したときの、物理的な揺らぎの影響や多数の回路や配線を集積化したときに生じるクロストークなどの相互干渉の影響を定量的に評価、予測し、集積化設計技術として構築する。
具体的には、まずナノ金属及びカーボンナノチューブ(CNT)やウォール(CNW)の電気伝導、特に高周波(110GHz)信号伝搬特性を明らかにする。次に、ナノデバイス、ナノ配線を集積化したときの回路性能、回路特性揺らぎ、ジャングルのような長距離多層配線構造内における100GHzの周波数成分を有する信号伝送の揺らぎやクロストーク評価を行い、ナノデバイス集積におけるシグナルインテグリティ研究を行う。アウトプットとして、信号伝送モデルや揺らぎモデルとして提示し、ナノメータデバイス集積化指針の構築を目指す。
1. 研究計画に沿って、平成18年度でナノ金属及びCNT/CNWの信号伝搬評価のために110GHzまでの高周波特性評価システムを立ち上げた。平成20年度では、引き続き金属配線について実際の測定を行い、de-embeddingの重要性を明確にするととともに2ポートおよび多ポートde-embedding手法を提案、実証した。
2. オンチップ伝送線路配線について、低消費電力化の可能な回路方式としてパルス化回路の試作と評価、プリエンファシス方式を取り入れて高速伝送化回路の設計、試作、評価を行った。回路試作は90nm CMOSプロセスを利用した。

  • Research Products

    (11 results)

All 2009 2008

All Journal Article (3 results) (of which Peer Reviewed: 3 results) Presentation (8 results)

  • [Journal Article] Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit2009

    • Author(s)
      Hirotaka SUGAWARA, Kenichi OKADA, Kazuya MASU
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics 92-A

      Pages: 1031-1038

    • Peer Reviewed
  • [Journal Article] Application of Correlation-based Regression Analysis for Improvement of Power Distribution Network2008

    • Author(s)
      Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu
    • Journal Title

      IEICE Transactions on Fundamentals 91-A

      Pages: 951-956

    • Peer Reviewed
  • [Journal Article] A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multi point-to-Multipoint On-Chip Communications2008

    • Author(s)
      Hiroyuki Ito, Makoto Kimura, K azuya Miyashita, Takahiro Ishii, Kenichi Okada, Kazuya Masu
    • Journal Title

      EEE Journal of Solid-State Circuits 141

      Pages: 1020-1029

    • Peer Reviewed
  • [Presentation] A 20 Gb/s 1:4 DEMUX with near-rail-to-rail logic swing in 90 nm CMOS process2009

    • Author(s)
      A. Mineyama, T. Suzuki, H. Ito, S. Amakawa, N. Ishihara, and K. Masu
    • Organizer
      IEEE Int. Workshop Sties on Signal Integrity and High-Speed Interconnects (IMWS2009-R9)
    • Place of Presentation
      Guadalajara, Mexico
    • Year and Date
      2009-02-20
  • [Presentation] A Simple Through-Only De-Embedding Method for On-Wafer S-Parameter Measurements up to 110 GHz2008

    • Author(s)
      Hiroyuki Ito, Kazuya Masu
    • Organizer
      IEEE MTT-S International Microwave Symposium2008 (IMS 2008)
    • Place of Presentation
      Atlanta
    • Year and Date
      20080615-20080620
  • [Presentation] "Non-invasive direct probing for on-chip voltage measurement2008

    • Author(s)
      Takashi Sato, Koh Yamanaga, and Kazuya Masu
    • Organizer
      International SoC design conference (ISOCC)
    • Place of Presentation
      International SoC design conference (ISOCC)
    • Year and Date
      2008-11-25
  • [Presentation] A MOS transistor array with pico-ampere order precision for accurate characterization of leakage current variation2008

    • Author(s)
      Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, and Kazuya Masu
    • Organizer
      A MOS transistor array with pico-ampere order precision for accurate characterization of leakage current variation
    • Place of Presentation
      Fukuoka,Japan
    • Year and Date
      2008-11-05
  • [Presentation] An Over-12-Gbps On-Chip Transmission Line Interconnect with a Pre-Emphasis Technique in 90 nm CMOS2008

    • Author(s)
      Kazuya Miyashita, Takahiro Ishii, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu
    • Organizer
      17th Conference on Electrical Performance of Electronic Packaging (EPEP)
    • Place of Presentation
      San Jose, California
    • Year and Date
      2008-10-28
  • [Presentation] Scaling Trend of Analog Integrated Circuit with Process Variations on Future Ultra Deep Submicron CMOS Technology2008

    • Author(s)
      Takao Oshita, Kazuo Tsutsui, Noboru Ishihara and Kazuya Masu
    • Organizer
      International Conference on Solid State Devices and Materials (SSDM)
    • Place of Presentation
      Tukuba
    • Year and Date
      2008-09-24
  • [Presentation] A simple de-embedding method for characterization of on-chip four-port networks2008

    • Author(s)
      Shuhei Amakawa, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu
    • Organizer
      Advanced Metallization Conference (AMC)
    • Place of Presentation
      Del Mar, California
    • Year and Date
      2008-09-23
  • [Presentation] An 8Gbps 2.5mW On-Chip Pulsed-Current-Mode Transmission Line Interconnect with a Stacked-Switch Tx2008

    • Author(s)
      Tomoaki Maekawa, Hiroyuki Ito, and Kazuya Masu
    • Organizer
      the 34th European Solid-State Circuits Conference
    • Place of Presentation
      Edinburgh, Scotland
    • Year and Date
      2008-09-18

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Published: 2010-06-11   Modified: 2016-04-21  

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