| Co-Investigator(Renkei-kenkyūsha) |
ISHIHARA Noboru 東京工業大学, 統合研究院, 特任教授 (20396641)
SATO Takashi 東京工業大学, 統合研究院, 特任教授 (20431992)
AMAKAWA Shuhei 東京工業大学, 統合研究院, 助教 (40431994)
ITO Hiroyuki 東京工業大学, 精密工学研究所, 助教 (40451992)
OKADA Kenichi 東京工業大学, 統合研究院, 助教 (70361772)
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| Research Abstract |
Nano-scale MOSFET has enabled a great number of circuit elements can be integrated into a single chip. So far, MOSFET has been miniaturized according to a scaling scheme, however, the chip size has not been reduced because more functions is required to be implemented on one chip; interconnect delays of long wires limit digital circuit performance. Interconnect design is a never-ending issue with CMOS LSI. For long wiring, we have developed transmission line interconnect (TLI).
In this project, we have developed (1) estimation of interconnect resource of nano-CMOS based on interconnect wire length distribution, (2) modeling of novel interconnect structure such as periodic scheme, multi-port analysis for cross-talk modeling, etc., (3) de-embedding method up to 100GHz which is essential in ultra high speed nano-CMOS circuit, (4) high-speed, low-latency, low-power, energy-efficient transmission line interconnect, which has been designed, fabricated and evaluated on 180nm, 90nm, and 65nm CMOS, and small area, low power, high-speed on-chip SER/DES circuits, (5) comparison of interconnect performance of transmission line, optical and wireless interconnects.
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