Study on design optimization of VLSI circuits for efficient approximate computing

2020 Fiscal Year Final Research Report

• Project/Area Number: 19K24341
• Research Category: Grant-in-Aid for Research Activity Start-up
• Allocation Type: Multi-year Fund
• Review Section: 1001:Information science, computer engineering, and related fields
• Research Institution: Nagoya University
• Principal Investigator: Masuda Yutaka 名古屋大学, 情報学研究科, 助教 (60845527)
• Project Period (FY): 2019-08-30 – 2021-03-31
• Keywords: 低消費電力設計 / 近似コンピューティング / クリティカルパス・アイソレーション / ビット幅削減

Outline of Final Research Achievements

This work proposed a design methodology that saves the power dissipation under　voltage over-scaling (VOS), which is one of the approximate computing techniques　aiming at low-power design. The key idea of the proposed design methodology is　to combine critical path isolation (CPI) and bit-width scaling (BWS) under the　constraint of computational quality. Thanks to the co-design optimization, the　proposed design dramatically reduces the supply voltage and power dissipation　while satisfying the quality constraint. Evaluation result show that CPI and BWS　are highly compatible, and they significantly enhance the efficacy of VOS. In a　case study of GPGPU processor, the proposed design saves the power dissipation
by 51.2% at most. This work also confirmed that the proposed design made the significant power savings even when operating at different PVTA corners.
Thus, such a variation-tolerant design can be useful for self-tuning design such as adaptive voltage scaling (AVS).

Free Research Field

集積回路の省電力設計

Academic Significance and Societal Importance of the Research Achievements

本研究は、「回路自身が計算品質を自律制御する」設計技術を見据えており、これは「最も悪い性能の回路に合わせる」従来設計技術とは本質的に異なるものである。本研究で構想する設計技術が完成した暁には、既存研究が抱える「性能ばらつきにより電力効率及び処理性能が大幅に低下する」問題を根本的に解決する。本研究では、計算品質を低電力動作下においても担保し、柔軟な自律制御を実現するための、集積回路の設計手法を提案した。評価実験により、提案設計が異なる動作環境 (電源電圧、温度など)において省電力効果を発揮できることを実験的に確認し、自律性能制御 VLSI (超大規模集積回路) への応用に期待できる成果を得た。