Research on Test Methodology for 3D Integrated SoCs

2011 Fiscal Year Final Research Report

• Project/Area Number: 21700059
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Nara Institute of Science and Technology
• Principal Investigator: YONEDA Tomokazu 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20359871)
• Project Period (FY): 2009 – 2011
• Keywords: テスト容易化設計 / 高品質遅延テスト / システムオンチップ / 3次元集積化

Research Abstract

The objective of this research is to find efficient methods of test generation and design for testability to achieve high quality and low cost test for 3D integrated SoCs. In this research, I focused attention on temperature during test and test data volume for 3D integrated SoCs. Consequently, I established a test generation method to reduce temperature-variation-induced delay test quality loss and a test cost optimization method that can achieve high quality delay test with low test data volume.

Research Products

• [Presentation] Faster-Than-At-Speed Test for Increased Test Quality and In-Field Reliability (2011)
  • Author(s): Tomokazu Yoneda, Keigo Hori, Michiko Inoue and Hideo Fujiwara
  • Organizer: IEEE International Test Conference(ITC' 11)
  • Place of Presentation: アメリカアナハイム
  • Year and Date: 2011-09-20
• [Presentation] Temperature-variation-aware test pattern optimization (2011)
  • Author(s): Tomokazu Yonedaノルウェートロンハイム., Makoto Nakao, Michiko Inoue, Yasuo Sato and Hideo Fujiwara
  • Organizer: IEEE European Test Symposium(ETS' 11)
  • Place of Presentation: ノルウェートロンハイム
  • Year and Date: 2011-05-25
• [Presentation] A Test Pattern Optimization to Reduce Spatial and Temporal Temperature Variations (2011)
  • Author(s): Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato and Hideo Fujiwara
  • Organizer: IEEE International Workshop on Reliability Aware System Design and Test(RASDAT' 11)
  • Place of Presentation: インドチェンナイ
  • Year and Date: 2011-01-06
• [Presentation] RedSOCs-3D : Thermal-safe Test Scheduling for 3D-Stacked SoC (2010)
  • Author(s): Fawnizu Azmadi Hussin, Thomas Edison Chua Yu, Tomokazu Yoneda and Hideo Fujiwara
  • Organizer: IEEE Asia Pacific Conference on Circuits and Systems(APCCAS2010)
  • Place of Presentation: マレーシアクアラルンプール
  • Year and Date: 2010-12-07
• [Presentation] Seed ordering and selection for high quality delay test (2010)
  • Author(s): Tomokazu Yoneda, Michiko Inoue, Akira Taketani and Hideo Fujiwara
  • Organizer: IEEE 19th Asian Test Symposium(ATS2010)
  • Place of Presentation: 中国上海
  • Year and Date: 2010-12-04
• [Presentation] Optimizing Delay Test Quality with a Limited Size of Test Set (2010)
  • Author(s): Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara
  • Organizer: IEEE European Test Symposium(ETS' 10)
  • Place of Presentation: チェコプラハ
  • Year and Date: 2010-05-27
• [Presentation] Thermal-uniformity aware x-filling to reduce temperature-induced delay variation for accurate at-speed testing (2010)
  • Author(s): Tomokazu Yoneda, Michiko Inoue, Yasuo Sato and Hideo Fujiwara
  • Organizer: 28th IEEE VLSI Test Symposium(VTS' 10)
  • Place of Presentation: アメリカサンタクルーズ
  • Year and Date: 2010-04-20
• [Presentation] Optimizing Delay Test Quality with a Limited Size of Test Set (2010)
  • Author(s): Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara
  • Organizer: IEEE International Workshop on Reliability Aware System Design and Test(RASDAT' 10)
  • Place of Presentation: インドバンガロール
  • Year and Date: 2010-01-08