2013 Fiscal Year Final Research Report
Nonvolatile-device-based PVT-variation-resilient VLSI system
| Project/Area Number |
22360137
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku University |
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Principal Investigator |
HANYU TAKAHIRO 東北大学, 電気通信研究所, 教授 (40192702)
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| Co-Investigator(Kenkyū-buntansha) |
NATSUI Masanori 東北大学, 電気通信研究所, 助教 (10402661)
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| Project Period (FY) |
2010-04-01 – 2014-03-31
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| Keywords | 回路設計技術 / 集積回路 / バラつき補正技術 / 新機能デバイス / 最適化技術 |
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| Research Abstract |
The aim of this research is to develop a new paradigm VLSI design methodology which relaxes design margin and realizes high-performance VLSI with high-dependability. In this research, we developed a MOS/magnetic-tunnel-junction-hybrid logic-circuit style for realizing a PVT-variation-aware VLSI processor with higher performance capability. For applying the proposed method to large-scale circuit structures, an optimization algorithm of circuit parameters based on evolutionary computation technique was also examined.
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