2012 Fiscal Year Final Research Report
Acceleration of Timing Analysis using Monte Carlo Methods
| Project/Area Number |
22360143
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Electron device/Electronic equipment
|
|---|
| Research Institution | Kyoto University |
|---|
Principal Investigator |
SATO Takashi 京都大学, 大学院・情報学研究科, 教授 (20431992)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
OCHI Hiroyuki 京都大学, 大学院・情報学研究科, 准教授 (40264957)
TSUTSUI Hiroshi 京都大学, 大学院・情報学研究科, 助教 (30402803)
|
|---|
| Project Period (FY) |
2010 – 2012
|
| Keywords | 集積回路設計技術 / CAD / タイミング解析 / モンテカルロ法 |
|---|
| Research Abstract |
Timing constraint is one of the most important objectives in advanced integrated circuit design. In this project, acceleration of the timing analysis is studied. Based on the measurements on test-chips, variability- and degradation-aware device models have been first proposed to accurately handle timing information of miniaturized devices. A new algorithm of timing analysis has then been implemented on a hardware, thorough which by more than ten times acceleration has been achieved while maintaining advantages of Monte Carlo based methods that can handle arbitrary delay distribution.
|
