2011 Fiscal Year Final Research Report
On-hip communication architecture for embedded multi-ore CPUs
| Project/Area Number |
22700051
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | Kyushu University (2011)
Toyohashi University of Technology (2010) |
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Principal Investigator |
SUGIHARA Makoto 九州大学, システムLSI研究センター, 准教授 (80373538)
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| Project Period (FY) |
2010 – 2011
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| Keywords | オンチップ通信 / ネットワークオンチップ / 組込みシステム / 通信アーキテクチャ合成 |
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| Research Abstract |
It is essential to satisfy the design requirements regarding chip area, performance, and energy consumption by optimizing a group of IP cores including CPU cores and its network when one utilizes multi-core CPUs as a component of application specific systems. It is important to build an EDA approach to automatically synthesize a communication mechanism as the number of transistors for a system is ever-increasing and the complexity of a system is increasing. In this work, we study a design methodology to synthesize on-chip communication architecture whose chip area, performance, and power consumption are optimized.
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Research Products
(4 results)
