2023 Fiscal Year Research-status Report
A HW-SW design and execution platform for sustainable edge-computing devices based on HDLRuby
| Project/Area Number |
22K11965
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| Research Institution | Ariake National College of Technology |
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Principal Investigator |
Gauthier Lovic 有明工業高等専門学校, 創造工学科, 教授 (90535717)
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| Co-Investigator(Kenkyū-buntansha) |
石川 洋平 有明工業高等専門学校, 創造工学科, 准教授 (50435476)
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| Project Period (FY) |
2022-04-01 – 2027-03-31
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| Keywords | EDA / HDL / High-Level Synthesis / HW/SW Co-Design / HW/SW Co-Simulation / Ruby Language / C Language / Graphical User Interface |
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| Outline of Annual Research Achievements |
This year, we finalized a new construct for describing hardware using structured programming code. We compared this construct with a commercial high-level synthesis tool and published the results, showing faster hardware with similar design effort.
Furthermore, we added the ability to integrate C and Ruby programs within HDLRuby hardware descriptions for co-simulation and co-design. The fully functional co-simulation engine was demonstrated with a UART keyboard and CRT display emulators.
Finally, to improve HDLRuby's accessibility, especially for students, we added two web-based graphical interfaces: one for visualizing simulation results and one for emulating an evaluation board interface (buttons, LEDs, oscilloscopes, etc.), accessible through a web browser during simulation.
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
In this research, we propose a hardware-software platform for sustainable edge-computing devices based on HDLRuby. We merged hardware and software within HDLRuby by adding a sequencer construct for describing hardware with software-like code and enabling software modules (in Ruby or C) within an HDLRuby description for co-design and co-simulation.
Future improvements currently in design phase, include introducing iterators and Ruby-like constructs for the sequencer and shared signals for abstracting communication protocols.
However, HDLRuby's industry adoption may be hindered if it cannot support proprietary IP libraries. Supporting external Verilog HDL or VHDL modules in HDLRuby would address this. Currently, HDLRuby can convert to these languages, but the reverse is not possible.
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| Strategy for Future Research Activity |
In terms of implementation, we plan to finalize the iterators and shared signals for higher-level software-like hardware descriptions and support the input of Verilog HDL files in the HDLRuby framework for co-simulation and co-design. We will also attempt to add support for dynamic reconfiguration, although it may be a less essential part of the project than initially thought.
So far, the majority of the chips described in HDLRuby have been physically implemented on FPGA boards. Therefore, we now plan to design an ASIC in HDLRuby and proceed to its physical implementation.
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| Causes of Carryover |
We had to set aside a portion of the income for travel expenses to attend the ICIAE conference held at the end of March, after it is possible to use 2023's income but before the beginning of the 2024 fiscal year.
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| Remarks |
HDLRuby and the hardware simulation result viewer HTMLWave are available online under the MIT license.
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