2013 Fiscal Year Final Research Report
A Study of High Dependability Reconfigurable Logic Architecture
| Project/Area Number |
23300017
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kumamoto University |
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Principal Investigator |
IIDA Masahiro 熊本大学, 自然科学研究科, 准教授 (70363512)
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| Co-Investigator(Kenkyū-buntansha) |
SUEYOSHI Toshinori 熊本大学, 自然科学研究科, 教授 (00117136)
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| Co-Investigator(Renkei-kenkyūsha) |
AMAGASAKI Motoki 熊本大学, 自然科学研究科, 助教 (50467974)
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| Project Period (FY) |
2011-04-01 – 2014-03-31
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| Keywords | リコンフィギャラブルシステム / ＦＰＧＡ / ディペンダブルシステム / ソフトエラー / SEU / LSI試作 |
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| Research Abstract |
System on a chip(SoC) market has become diversified, with the development of high integration density, VLSI designs are becoming more complex and longer design cycles are required. Reconfigurable logic devices such as field-programmable gate arrays (FPGAs) are used widely as a solution to the above problems. However, FPGA which has the large quantity of configuration memory bits used for user logic becomes undependable circuits when soft error such as single event upset (SEU) occurs.
In order to solve the above problems, high dependable reconfigurable logic technology is researched in this research. We proposed fault-tolerant FPGA(FT-FPGA) architectures and their computer-aid design (CAD) for intellectual property (IP) cores for SoC. In addition, we developed prototype chip of FT-FPGA. We confirmed that by a series of evaluation of this chip, FT-FPGA has the capability of avoidance of hard and soft errors, automatic repair of user circuit.
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