2013 Fiscal Year Final Research Report

Charge and discharge circuit for double layer capacitor

Research Project

Project/Area Number	23560347
Research Category	Grant-in-Aid for Scientific Research (C)
Allocation Type	Multi-year Fund
Section	一般
Research Field	Power engineering/Power conversion/Electric machinery
Research Institution	Tomakomai National College of Technology
Principal Investigator	UEDA Shigeta 苫小牧工業高等専門学校, その他部局等, 教授 (40390380)
Project Period (FY)	2011 – 2013
Keywords	電気二重層コンデンサ / 充電回路 / 放電回路
Research Abstract	The rated voltage of double layer capacitor(EDLC) is relatively low. In high voltage applications many EDLCs are connected in series. In this case high voltage power source for charge is required and voltage imbalance of EDLCs is caused. A solution for such problem is proposed using variable connection scheme. Many EDLCs are connected in parallel through diodes in charging, and these are connected in series through several mechanical relays in discharging. Proposed scheme is evaluated in test equipment which is consisted of Eight EDLCs rated specifications of 233F,15V, sixteen diodes, seven mechanical relays and dc motor. Time of discharge is 1900 seconds at load of 80W. Voltge imbalance of EDLCs is absorbed within plus or minus 1%. The high energy efficiency between charge and discharge from 70% to 80% is obtained.